2001-12-22 01:33:28 +03:00
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/* $NetBSD: if_eireg.h,v 1.2 2001/12/21 22:33:28 bjh21 Exp $ */
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2001-03-20 02:58:12 +03:00
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/*
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* 2000 Ben Harris
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*
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* This file is in the public domain.
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*/
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/*
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* if_eireg.h - register definitions etc for the Acorn Ether1 card
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*/
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#ifndef _IF_EIREG_H_
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#define _IF_EIREG_H_
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/*
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* The card has three address spaces. The ROM is mapped into the
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2001-12-22 01:33:28 +03:00
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* bottom 32 bytes of SYNC address space, and contains the
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2001-03-20 02:58:12 +03:00
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* expansion card ID information and the Ethernet address. There is a
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2001-12-22 01:33:28 +03:00
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* pair of write-only registers at the start of the FAST address
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2001-03-20 02:58:12 +03:00
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* space. One of these performs miscellaneous control functions, and
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* the other acts as a page selector for the board memory. The board
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* has 64k of RAM, and 4k pages of this can be mapped at offset 0x2000
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* in the FAST space by writing the page number to the page register.
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* The 82586 has access to the whole of this memory and (I believe)
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* sees it as the top 64k of its address space.
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*/
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/* Registers in the board's control space */
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#define EI_PAGE 0
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#define EI_CONTROL 1
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2001-12-22 01:33:28 +03:00
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#define EI_CTL_RST 0x01 /* Reset */
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#define EI_CTL_LB 0x02 /* Loop-back */
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#define EI_CTL_CA 0x04 /* Channel Attention */
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#define EI_CTL_CLI 0x08 /* Clear Interrupt */
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2001-03-20 02:58:12 +03:00
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/* Offset of base of memory in bus_addr_t units */
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#define EI_MEMOFF 0x2000
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/*
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* All addresses within board RAM are in bytes of actual RAM. RAM is
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2001-12-22 01:33:28 +03:00
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* 16 bits wide, and can only be accessed by word transfers
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2001-03-20 02:58:12 +03:00
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* (bus_space_xxx_2).
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*/
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#define EI_MEMSIZE 0x10000
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#define EI_MEMBASE (0x1000000 - EI_MEMSIZE)
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#define EI_PAGESIZE 0x1000
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#define EI_NPAGES (EI_MEMSIZE / EI_PAGESIZE)
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#define ei_atop(a) (((a) % EI_MEMSIZE) / EI_PAGESIZE)
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#define ei_atopo(a) ((a) % EI_PAGESIZE)
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#define EI_SCP_ADDR IE_SCP_ADDR % EI_MEMSIZE
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2001-12-22 01:33:28 +03:00
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/*
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* The ROM on the Ether1 is a bit oddly wired, in that the interrupt
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* line is wired up as the high-order address line, so as to allow the
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* interrupt status bit the the first byte to reflect the actual
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* interrupt status.
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*/
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#define EI_ROMSIZE 0x20
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/* First eight bytes are standard extended podule ID. */
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#define EI_ROM_HWREV 0x08
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#define EI_ROM_EADDR 0x09
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#define EI_ROM_CRC 0x1c
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2001-03-20 02:58:12 +03:00
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#endif
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