2008-04-29 00:22:51 +04:00
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/* $NetBSD: lxtphyreg.h,v 1.2 2008/04/28 20:23:53 martin Exp $ */
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1998-10-24 04:33:17 +04:00
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_LXTPHYREG_H_
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#define _DEV_MII_LXTPHYREG_H_
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/*
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* LXT970 registers.
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*/
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#define MII_LXTPHY_MIRROR 0x10 /* Mirror register */
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/* All bits user-defined */
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#define MII_LXTPHY_IER 0x11 /* Interrupt Enable Register */
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#define IER_MIIDRVLVL 0x0008 /* Rediced MII driver levels */
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#define IER_LNK_CRITERIA 0x0004 /* Enhanced Link Loss Criteria */
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#define IER_INTEN 0x0002 /* Interrupt Enable */
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#define IER_TINT 0x0001 /* Force Interrupt */
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#define MII_LXTPHY_ISR 0x12 /* Interrupt Status Register */
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#define ISR_MINT 0x8000 /* MII Interrupt Pending */
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#define ISR_XTALOK 0x4000 /* Clocks OK */
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#define MII_LXTPHY_CONFIG 0x13 /* Configuration Register */
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#define CONFIG_TXMIT_TEST 0x4000 /* 100base-T Transmit Test */
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#define CONFIG_REPEATER 0x2000 /* Repeater Mode */
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#define CONFIG_MDIO_INT 0x1000 /* Enable intr signalling on MDIO */
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#define CONFIG_TPLOOP 0x0800 /* Disable 10base-T Loopback */
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#define CONFIG_SQE 0x0400 /* Enable SQE */
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#define CONFIG_DISJABBER 0x0200 /* Disable Jabber */
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#define CONFIG_DISLINKTEST 0x0100 /* Disable Link Test */
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#define CONFIG_LEDC1 0x0080 /* LEDC configuration */
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#define CONFIG_LEDC0 0x0040 /* ... */
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/* 0 0 LEDC indicates collision */
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/* 0 1 LEDC is off */
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/* 1 0 LEDC indicates activity */
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/* 1 1 LEDC is on */
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#define CONFIG_ADVTXCLK 0x0020 /* Advance TX clock */
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#define CONFIG_5BSYMBOL 0x0010 /* 5-bit Symbol mode */
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#define CONFIG_SCRAMBLER 0x0008 /* Bypass scrambler */
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#define CONFIG_100BASEFX 0x0004 /* 100base-FX */
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#define CONFIG_TXDISCON 0x0001 /* Disconnect TP transmitter */
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#define MII_LXTPHY_CSR 0x14 /* Chip Status Register */
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#define CSR_LINK 0x2000 /* Link is up */
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#define CSR_DUPLEX 0x1000 /* Full-duplex */
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#define CSR_SPEED 0x0800 /* 100Mbps */
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#define CSR_ACOMP 0x0400 /* Autonegotiation complete */
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#define CSR_PAGERCVD 0x0200 /* Link page received */
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#define CSR_LOWVCC 0x0004 /* Low Voltage Fault */
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#endif /* _DEV_MII_LXTPHYREG_H_ */
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