109 lines
4.3 KiB
C
109 lines
4.3 KiB
C
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/* $NetBSD: swreg.h,v 1.1 2000/06/26 19:54:09 pk Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register map for the Sun3 SCSI Interface (si)
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* The first part of this register map is an NCR5380
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* SCSI Bus Interface Controller (SBIC). The rest is a
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* DMA controller and custom logic for the OBIO interface (3/50,3/60,4/110)
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*
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* Modified for Sun 4 systems by Jason R. Thorpe <thorpej@NetBSD.ORG>.
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*/
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/*
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* Note that the obio version on the 4/1xx (the so-called "SCSI Weird", or
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* "sw" controller) is laid out a bit differently, and hence the evilness
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* with unions. Also, the "sw" doesn't appear to have a FIFO.
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*/
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#if __for_reference_only__
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struct sw_regs {
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/*
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* Am5380 Register map (no padding). See dev/ic/ncr5380reg.h
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*/
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struct ncr5380regs {
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u_char r[8];
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} sci;
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/* DMA controller registers on OBIO */
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u_int dma_addr; /* dma address */
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u_int dma_count; /* dma count */
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u_int pad0; /* no-existent register */
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u_int sw_csr; /* sw control/status */
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u_int bpr; /* sw byte pack */
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};
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#endif
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/*
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* Size of NCR5380 registers located at the bottom of the register bank.
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*/
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#define NCR5380REGS_SZ 8
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/*
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* Register definition for the `sw' OBIO controller
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*/
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#define SWREG_DMA_ADDR (NCR5380REGS_SZ + 0)
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#define SWREG_DMA_CNT (NCR5380REGS_SZ + 4)
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#define SWREG_CSR (NCR5380REGS_SZ + 12)
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#define SWREG_BPR (NCR5380REGS_SZ + 16)
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#define SWREG_BANK_SZ (NCR5380REGS_SZ + 20)
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/*
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* Status Register.
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* Note:
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* (r) indicates bit is read only.
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* (rw) indicates bit is read or write.
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* (v) vme host adaptor interface only.
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* (o) sun3/50 onboard host adaptor interface only.
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* (b) both vme and sun3/50 host adaptor interfaces.
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*/
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#define SW_CSR_DMA_ACTIVE 0x8000 /* (r,o) dma transfer active */
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#define SW_CSR_DMA_CONFLICT 0x4000 /* (r,b) reg accessed while dmaing */
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#define SW_CSR_DMA_BUS_ERR 0x2000 /* (r,b) bus error during dma */
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#define SW_CSR_ID 0x1000 /* (r,b) 0 for 3/50, 1 for SCSI-3, */
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/* 0 if SCSI-3 unmodified */
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#define SW_CSR_FIFO_FULL 0x0800 /* (r,b) fifo full */
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#define SW_CSR_FIFO_EMPTY 0x0400 /* (r,b) fifo empty */
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#define SW_CSR_SBC_IP 0x0200 /* (r,b) sbc interrupt pending */
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#define SW_CSR_DMA_IP 0x0100 /* (r,b) dma interrupt pending */
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#define SW_CSR_DMA_EN 0x0010 /* (rw,v) dma/interrupt enable */
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#define SW_CSR_SEND 0x0008 /* (rw,b) dma dir, 1=to device */
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#define SW_CSR_INTR_EN 0x0004 /* (rw,b) interrupts enable */
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#define SW_CSR_FIFO_RES 0x0002 /* (rw,b) inits fifo, 0=reset */
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#define SW_CSR_SCSI_RES 0x0001 /* (rw,b) reset sbc and udc, 0=reset */
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