100 lines
4.2 KiB
C
100 lines
4.2 KiB
C
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/* $NetBSD: lptreg.h,v 1.1 1996/11/09 03:52:52 chuck Exp $ */
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/*-
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* Copyright (c) 1996 Steve Woodford
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Steve Woodford
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* MVME147 Parallel Port Register Definitions
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* Copyright (c) 1996 Steve Woodford
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*/
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/*
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* The mvme147's PCC chip has two status/control registers for the
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* printer port:
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*
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* sys_pcc->pr_int Printer Interrupt Control Register
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* 0 - 2 Interrupt Level
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* 3 Interrupt Enable
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* 4 ACK Polarity. If set, falling edge of ACK generates
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* the interrupt. If clear, rising edge of ACK generates
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* the interrupt.
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* 5 Indicates an ACK interrupt in progress. Cleared by
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* writing a one, or disabling lpt interrupts.
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* 6 Indicates a FAULT interrupt. Set on falling edge
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* of printer's fault signal. Cleared by writing a one.
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* 7 Printer Interrupt in progress. Basically just the
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* logical OR of bits 5 and 6.
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*/
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#define LPI_ENABLE (1 << 3)
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#define LPI_ACKPOL (1 << 4)
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#define LPI_ACKINT (1 << 5)
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#define LPI_FAULTINT (1 << 6)
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#define LPI_INTERRUPT (1 << 7)
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/*
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* sys_pcc->pr_cr Printer Control Register
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* 0 Selects auto or manual strobe mode. When low, strobe
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* is automatically generated by a write to the printer
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* data register. When set, strobe must be generated
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* manually using bit 2 of this register.
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* 1 Controls strobe timing in auto mode. When low, strobe
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* time is 6.4uS. When high, strobe time is 1.6uS.
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* 2 Controls strobe in manual mode.
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* 3 Control Input Prime signal. When set, Input Prime
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* is activated.
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*
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* Two other registers which are not addressed via the global PCC structure,
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* live at 0xfffe2800. This address is virtualised and passed to the driver
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* in the pcc_attach_args structure:
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*/
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#define LPC_STROBE_MODE (1 << 0)
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#define LPC_FAST_STROBE (1 << 1)
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#define LPC_STROBE (1 << 2)
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#define LPC_INPUT_PRIME (1 << 3)
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/*
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* Union of data and status registers. Write to access the data register.
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* Read to access the status register.
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*/
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union lpt_regs {
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volatile u_char pr_data; /* Write only data register */
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volatile u_char pr_status; /* Read only status register */
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};
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/*
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* Access macros for the status register
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*/
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#define LPS_BUSY (1 << 3)
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#define LPS_PAPER_EMPTY (1 << 4)
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#define LPS_SELECT (1 << 5)
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#define LPS_FAULT (1 << 6)
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#define LPS_ACK (1 << 7)
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