147 lines
5.3 KiB
C
147 lines
5.3 KiB
C
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/* $NetBSD: clockreg.h,v 1.1.1.1 1998/06/09 07:53:05 dbj Exp $ */
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/*
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* Copyright (c) 1997 Rolf Grossmann
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Rolf Grossmann.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* NeXT clock registers
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*/
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struct scr2 { /* zeroed at power-on, read/write */
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u_int s_dsp_reset : 1,
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s_dsp_block_end : 1,
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s_dsp_unpacked : 1,
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s_dsp_mode_B : 1,
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s_dsp_mode_A : 1,
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s_remote_int : 1,
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s_local_int : 2, /* in fact :1 reserved and :1 local_int? */
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s_dram_256K : 4,
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s_dram_1M : 4,
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s_timer_on_ipl7 : 1,
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s_rom_wait_states : 3,
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s_rom_1M : 1,
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s_rtdata : 1,
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s_rtclk : 1,
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s_rtce : 1,
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s_rom_overlay : 1,
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s_dsp_int_en : 1,
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s_dsp_mem_en : 1,
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s_reserved : 4,
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s_led : 1;
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};
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#define SCR2_DSP_RESET 0x80000000
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#define SCR2_DSP_BLOCK_END 0x40000000
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#define SCR2_DSP_UNPACKED 0x20000000
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#define SCR2_DSP_MODE_B 0x10000000
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#define SCR2_DSP_MODE_A 0x08000000
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#define SCR2_REMOTE_INT 0x04000000
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#define SCR2_LOCAL_INT 0x01000000
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#define SCR2_DRAM_256K 0x00100000
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#define SCR2_DRAM_1M 0x00010000
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#define SCR2_TIMER_ON_IPL7 0x00008000
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#define SCR2_ROM_WAITSTATES 0x00007000
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#define SCR2_ROM_1M 0x00000800
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#define SCR2_RTDATA 0x00000400
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#define SCR2_RTCLK 0x00000200
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#define SCR2_RTCE 0x00000100
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#define SCR2_ROM_OVERLAY 0x00000080
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#define SCR2_DSP_IE 0x00000040
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#define SCR2_MEM_EN 0x00000020
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#define SCR2_LED 0x00000001
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/* real time clock -- old is MC68HC68T1 chip, new is MCS1850 chip */
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#define RTC_RAM 0x00 /* both */
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#define RTC_SEC 0x20 /* old BCD coded date*/
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#define RTC_MIN 0x21
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#define RTC_HRS 0x22
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#define RTC_DAY 0x23
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#define RTC_DATE 0x24
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#define RTC_MON 0x25
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#define RTC_YR 0x26
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#define RTC_ALARM_SEC 0x28
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#define RTC_ALARM_MIN 0x29
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#define RTC_ALARM_HR 0x2a
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#define RTC_CNTR0 0x20 /* new */
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#define RTC_CNTR1 0x21
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#define RTC_CNTR2 0x22
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#define RTC_CNTR3 0x23
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#define RTC_ALARM0 0x24
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#define RTC_ALARM1 0x25
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#define RTC_ALARM2 0x26
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#define RTC_ALARM3 0x27
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#define RTC_STATUS 0x30 /* both */
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#define RTC_CONTROL 0x31 /* both */
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#define RTC_INTRCTL 0x32 /* old */
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/* bits in RTC_STATUS */
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#define RTC_NEW_CLOCK 0x80 /* new: set in new clock chip */
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#define RTC_FTU 0x10 /* both: set when powered up but uninitialized */
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#define RTC_INTR 0x08 /* new: interrupt asserted */
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#define RTC_LOW_BATT 0x04 /* new: low battery */
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#define RTC_ALARM 0x02 /* new: alarm interrupt */
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#define RTC_RPD 0x01 /* new: request to power down */
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/* bits in RTC_CONTROL */
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#define RTC_START 0x80 /* both: start counters */
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#define RTC_STOP 0x00 /* both: stop counters */
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#define RTC_XTAL 0x30 /* old: xtal: line = 0, sel0 = sel1 = 1 */
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#define RTC_AUTO_PON 0x20 /* new: auto poweron after power fail */
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#define RTC_AE 0x10 /* new: alarm enable */
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#define RTC_AC 0x08 /* new: alarm clear */
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#define RTC_FTUC 0x04 /* new: first time up clear */
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#define RTC_LBE 0x02 /* new: low battery enable */
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#define RTC_RPDC 0x01 /* new: request to power down clear */
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/* bits in RTC_INTRCTL */
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#define RTC_PDOWN 0x40 /* both: power down, bit in RTC_CONTROL on new chip */
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#define RTC_64HZ 0x06 /* old: periodic select = 64 Hz */
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#define RTC_128HZ 0x05 /* old: periodic select = 128 Hz */
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#define RTC_512HZ 0x03 /* old: periodic select = 512 Hz */
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/* RTC address byte format */
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#define RTC_WRITE 0x80
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#define RTC_ADRS 0x3f
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struct timer_reg {
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u_char msb;
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u_char lsb;
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u_char pad0;
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u_char pad1;
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u_char csr;
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};
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/* timer register */
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#define TIMER_ENABLE 0x80
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#define TIMER_UPDATE 0x40
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#define TIMER_MAX 0xffff /* Maximum value of timer */
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