2007-12-03 18:33:00 +03:00
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/* $NetBSD: intr.h,v 1.19 2007/12/03 15:34:22 ad Exp $ */
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1999-05-30 06:37:10 +04:00
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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2004-03-14 21:18:54 +03:00
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#ifndef _SPARC64_INTR_H_
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#define _SPARC64_INTR_H_
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#include <machine/cpuset.h>
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1999-05-30 06:37:10 +04:00
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/* XXX - arbitrary numbers; no interpretation is defined yet */
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2000-08-24 01:35:56 +04:00
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#define IPL_NONE 0 /* nothing */
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#define IPL_SOFTCLOCK 1 /* timeouts */
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2007-12-03 18:33:00 +03:00
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#define IPL_SOFTBIO 1 /* block I/O */
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2000-08-24 01:35:56 +04:00
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#define IPL_SOFTNET 1 /* protocol stack */
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#define IPL_SOFTSERIAL 4 /* serial */
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2006-05-04 16:18:54 +04:00
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#define IPL_VM PIL_VM /* memory allocation */
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2000-08-24 01:35:56 +04:00
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#define IPL_SCHED PIL_SCHED /* scheduler */
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#define IPL_HIGH PIL_HIGH /* everything */
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2004-03-14 21:18:54 +03:00
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#define IPL_HALT 5 /* cpu stop-self */
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#define IPL_PAUSE 13 /* pause cpu */
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2006-10-06 12:44:59 +04:00
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#define IPL_FDSOFT PIL_FDSOFT /* floppy */
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2004-03-14 21:18:54 +03:00
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2006-09-18 12:18:47 +04:00
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void save_and_clear_fpstate(struct lwp *);
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2004-03-14 21:18:54 +03:00
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#if defined(MULTIPROCESSOR)
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2004-05-20 04:56:12 +04:00
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void sparc64_ipi_init (void);
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SMP cleanup. provide support for multiple CPUs in DDB. (SMP itself
is still not working.)
cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
does the same) and also implement "mach cpu N" to switch to
another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
if DDB is configured, enable it to save the passed-in trapframe
to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
the address and argument of the to be called function. (the
argument right now is the address of ipi_tlb_args variable, and
part of the reason why only one CPU can send IPI's at a time.)
don't wait forever for an IPI to complete. some of this is
from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
smp_tlb_flush_ctx() and smp_tlb_flush_all(). the other end may
not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
the debugger using the normal breakpoint trap. these cpus usually
lose the race in db_interface.c:db_suspend_others() and end up
calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
%tpc is at the sparc64_ipi_pause_trap_point and if so, call
"done" not "retry"
- rework cpu_switch slightly: save the passed-in lwp instead of
using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well. from petrov.
- in cpu_exit(), fix a load register confusion. from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages
2006-09-13 15:35:53 +04:00
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int sparc64_ipi_halt_thiscpu (void *);
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int sparc64_ipi_pause_thiscpu (void *);
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2006-09-18 12:18:47 +04:00
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void sparc64_ipi_drop_fpstate (void *);
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void sparc64_ipi_save_fpstate (void *);
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2007-05-17 18:51:11 +04:00
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void sparc64_ipi_nop (void *);
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SMP cleanup. provide support for multiple CPUs in DDB. (SMP itself
is still not working.)
cpu.h:
- add a pointer for DDB regs in SMP environment to struct cpu_info
- remove the #defines for mp_pause_cpus() and mp_resume_cpus()
cpuset.h:
- remove CPUSET_ALL() and rename CPUSET_ALL_BUT() to CPUSET_EXCEPT()
from petrov.
db_machdep.h:
- rename the members of db_regs_t to be the same as sparc
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- redo DDB_REGS to no longer be a pointer to a fixed data structure
but to one allocated per-cpu when ddb is entered
- move a bunch of prototypes in here
intr.h:
- remove SPARC64_IPI_* macros, no longer used
db_interface.c:
- change "db_regs_t ddb_regs" to "db_regs_t *ddb_regp" and change
all references to suit
- make "nil" a 64 bit entity
- change the ddb register access methods to work in multiprocessor
environment, it is now very much like sparc does it
- in kdb_trap() avoid accessing ddb_regp when it is NULL
- update several messages to include the cpu number
- unpause other cpus much later when resuming from ddb
- rename db_lock() to db_lock_cmd(), as the sparc-like code has
db_lock as a simple lock
- remove "mach cpus" command, and replace it with "mach cpu" (which
does the same) and also implement "mach cpu N" to switch to
another cpus saved trapframe
db_trace.c:
- update for the ddb_regs -> ddb_regp change
genassym.cf:
- add TF_KSTACK as offsetof(struct trapframe64, tf_kstack)
ipifuncs.c:
- overhaul extensively
- remove all normal interrupt handlers as IPI's, we now handle
them all specially in locore.s:interrupt_vector
- add a simplelock around all ipi functions - it's not safe for
multiple cpus to be sending IPI's to each other right now
- rename sparc64_ipi_pause() to sparc64_ipi_pause_thiscpu() and,
if DDB is configured, enable it to save the passed-in trapframe
to a db_regs_t for this cpu's saved DDB registers.
- remove the "ipimask" system (SPARC64_IPI_* macros) and instead
pass functions directly
- in sparc64_send_ipi() always set the interrupt arguments to 0,
the address and argument of the to be called function. (the
argument right now is the address of ipi_tlb_args variable, and
part of the reason why only one CPU can send IPI's at a time.)
don't wait forever for an IPI to complete. some of this is
from petrov.
- rename sparc64_ipi_{halt,pause,resume}_cpus() to
mp_{halt,pause,resume}_cpus()
- new function mp_cpu_is_paused() used to avoid access missing
saved DDB registers
- actually broadcast the flush in smp_tlb_flush_pte(),
smp_tlb_flush_ctx() and smp_tlb_flush_all(). the other end may
not do anything yet in the pte/ctx cases yet...
kgdb_machdep.c:
- rework for changed member names in db_regs_t.
locore.s:
- shave an instruction from syscall_setup() (set + ld -> sethi + ld)
- remove some old dead debug code
- add new sparc64_ipi_halt IPI entry point, it just calls the C
vector to shutdown.
- add new sparc64_ipi_pause IPI entry point, which just traps into
the debugger using the normal breakpoint trap. these cpus usually
lose the race in db_interface.c:db_suspend_others() and end up
calling the C vector sparc64_ipi_pause_thiscpu().
- add #if 0'ed code to sparc64_ipi_flush_{pte,ctx}() IPI entry
points to call the sp_ version of these functions.
- in rft_kernel (return from trap, kernel), check to see if the
%tpc is at the sparc64_ipi_pause_trap_point and if so, call
"done" not "retry"
- rework cpu_switch slightly: save the passed-in lwp instead of
using the one in curlwp
- in cpu_loadproc(), save the new lwp not the old lwp, to curlwp
- in cpu_initialize(), set %tl to zero as well. from petrov.
- in cpu_exit(), fix a load register confusion. from petrov.
- change some "set" in delay branch to "mov".
machdep.c:
- deal with function renames
pmap.c:
- remove a spurious space
trap.c:
- remove unused "trapstats" variable
- add cpu number to a couple of messages
2006-09-13 15:35:53 +04:00
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void mp_halt_cpus (void);
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void mp_pause_cpus (void);
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void mp_resume_cpus (void);
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int mp_cpu_is_paused (cpuset_t);
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2004-03-14 21:18:54 +03:00
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#endif
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1999-05-30 06:37:10 +04:00
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2004-03-14 21:18:54 +03:00
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#endif /* _SPARC64_INTR_H_ */
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