294 lines
10 KiB
C
294 lines
10 KiB
C
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/* $NetBSD: rpb.h,v 1.1 1995/02/13 23:07:54 cgd Exp $ */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic, Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* From DEC 3000 300/400/500/600/800 System Programmer's Manual,
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* EK-D3SYS-PM.A01.
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*/
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/*
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* HWRPB (Hardware Restart Parameter Block).
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*/
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#define HWRPB_ADDR 0x10000000 /* virtual address, at boot */
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#ifndef ASSEMBLER
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struct rpb {
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struct restart_blk *rpb; /* 0: HWRPB phys. address. */
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char rpb_magic[8]; /* 8: "HWRPB" (in ASCII) */
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u_int64_t rpb_version; /* 10 */
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u_int64_t rpb_size; /* 18: HWRPB size in bytes */
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u_int64_t rpb_primary_cpu_id; /* 20 */
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u_int64_t rpb_page_size; /* 28: (8192) */
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u_int64_t rpb_phys_addr_size; /* 30: (34) */
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u_int64_t rpb_max_asn; /* 38: (16) */
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char rpb_ssn[16]; /* 40: only first 10 valid */
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#define ST_ADU 1
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#define ST_DEC_4000 2
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#define ST_DEC_7000 3
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#define ST_DEC_3000_500 4
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#define ST_DEC_2000_300 6
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#define ST_DEC_3000_300 7
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u_int64_t rpb_type; /* 50: */
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#define SYSTEM_VAR_MPCAP 0x0001 /* multiprocessor */
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#define SYSTEM_VAR_CONSOLE 0x001e /* console hardware mask */
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#define SYSTEM_VAR_CNSL_DETACHED 0x0002
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#define SYSTEM_VAR_CNSL_EMBEDDED 0x0004
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#define SYSTEM_VAR_POWERFAIL 0x00e0 /* powerfail mask */
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#define SYSTEM_VAR_PF_UNITED 0x0020
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#define SYSTEM_VAR_PF_SEPARATE 0x0040
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#define SYSTEM_VAR_PF_BBACKUP 0x0060
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#define SYSTEM_VAR_PF_ACTION 0x0100 /* 1 -> restart all processors
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* on powerfail
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* 0 -> only primary
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*/
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#define SYSTEM_VAR_GRAPHICS 0x0200 /* graphic engine present */
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#define SYSTEM_VAR_mbz 0xfffffffffffffc00 /* 10:64 -- must be zero */
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u_int64_t rpb_variation; /* 58 */
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char rpb_revision[8]; /* 60; only first 4 valid */
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u_int64_t rpb_intr_freq; /* 68; scaled by 4096 */
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u_int64_t rpb_cc_freq; /* 70: cycle cntr frequency */
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vm_offset_t rpb_vptb; /* 78: */
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u_int64_t rpb_reserved_arch; /* 80: */
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vm_offset_t rpb_tbhint_off; /* 88: */
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u_int64_t rpb_pcs_cnt; /* 90: */
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u_int64_t rpb_pcs_size; /* 98; pcs size in bytes */
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vm_offset_t rpb_pcs_off; /* A0: offset to pcs info */
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u_int64_t rpb_ctb_cnt; /* A8: console terminal */
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u_int64_t rpb_ctb_size; /* B0: ctb size in bytes */
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vm_offset_t rpb_ctb_off; /* B8: offset to ctb */
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vm_offset_t rpb_crb_off; /* C0: offset to crb */
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vm_offset_t rpb_memdat_off; /* C8: memory data offset */
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vm_offset_t rpb_condat_off; /* D0: config data offset */
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vm_offset_t rpb_fru_off; /* D8: FRU table offset */
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long (*rpb_save_term)(); /* E0: terminal save */
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long rpb_save_term_val; /* E8: */
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long (*rpb_rest_term)(); /* F0: terminal restore */
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long rpb_rest_term_val; /* F8: */
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long (*rpb_restart)(); /* 100: restart */
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long rpb_restart_val; /* 108: */
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u_int64_t rpb_reserve_os; /* 110: */
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u_int64_t rpb_reserve_hw; /* 118: */
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u_int64_t rpb_checksum; /* 120: HWRPB checksum */
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u_int64_t rpb_rxrdy; /* 128: receive ready */
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u_int64_t rpb_txrdy; /* 130: transmit ready */
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vm_offset_t rpb_dsrdb_off; /* 138: HWRPB + DSRDB offset */
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u_int64_t rpb_tbhint[8]; /* 149: TB hint block */
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};
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#ifdef KERNEL
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extern struct rpb *hwrpb;
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#endif
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/*
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* PCS: Per-CPU information.
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*/
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struct pcs {
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u_int8_t pcs_hwpcb[128]; /* 0: PAL dependent */
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#define PCS_BIP 0x000001 /* boot in progress */
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#define PCS_RIP 0x000002 /* restart in progress */
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#define PCS_PA 0x000004 /* processor available */
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#define PCS_PP 0x000008 /* processor present */
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#define PCS_OH 0x000010 /* user halted */
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#define PCS_CV 0x000020 /* context valid */
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#define PCS_PV 0x000040 /* PALcode valid */
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#define PCS_PMV 0x000080 /* PALcode memory valid */
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#define PCS_PL 0x000100 /* PALcode loaded */
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#define PCS_PE 0x000200 /* primary eligible (SMP) */
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#define PCS_HALT_REQ 0xff0000 /* halt request mask */
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#define PCS_HALT_DEFAULT 0x000000
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#define PCS_HALT_SAVE_EXIT 0x010000
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#define PCS_HALT_COLD_BOOT 0x020000
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#define PCS_HALT_WARM_BOOT 0x030000
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#define PCS_HALT_STAY_HALTED 0x040000
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#define PCS_mbz 0xffffffffff000000 /* 24:63 -- must be zero */
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u_int64_t pcs_flags; /* 80: */
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u_int64_t pcs_pal_memsize; /* 88: PAL memory size */
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u_int64_t pcs_pal_scrsize; /* 90: PAL scratch size */
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vm_offset_t pcs_pal_memaddr; /* 98: PAL memory addr */
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vm_offset_t pcs_pal_scraddr; /* A0: PAL scratch addr */
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struct {
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u_int64_t
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pcs_alpha : 8, /* alphabetic char 'a' - 'z' */
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#define PAL_TYPE_STANDARD 0
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#define PAL_TYPE_ULTRIX 1
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pcs_pal_type : 8, /* PALcode type:
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* 0 == standard
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* 1 == Ultrix
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* 2-127 DIGITAL reserv.
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* 128-255 non-DIGITAL reserv.
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*/
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sbz1 : 16,
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pcs_proc_cnt : 7, /* Processor count */
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sbz2 : 25;
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} pcs_pal_rev; /* A8: */
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#define pcs_alpha pcs_pal_rev.alpha
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#define pcs_pal_type pcs_pal_rev.pal_type
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#define pcs_proc_cnt pcs_pal_rev.proc_cnt
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u_int64_t pcs_proc_type; /* B0: (always 2) */
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struct {
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u_int64_t
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pcs_vaxfp : 1, /* Vax floating point */
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pcs_ieeefp : 1, /* IEEE floating point */
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pcs_reserved : 62;
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} pcs_proc_var; /* B8: */
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#define pcs_vaxfp pcs_proc_var.pcs_vaxfp
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#define pcs_ieeefp pcs_proc_var.pcs_ieeefp
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char pcs_proc_revision[8]; /* C0: only first 4 valid */
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char pcs_proc_sn[16]; /* C8: only first 10 valid */
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vm_offset_t pcs_machcheck; /* D8: mach chk phys addr. */
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u_int64_t pcs_machcheck_len; /* E0: length in bytes */
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vm_offset_t pcs_halt_pcbb; /* E8: phys addr of halt PCB */
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vm_offset_t pcs_halt_pc; /* F0: halt PC */
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u_int64_t pcs_halt_ps; /* F8: halt PS */
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u_int64_t pcs_halt_r25; /* 100: halt argument list */
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u_int64_t pcs_halt_r26; /* 108: halt return addr list */
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u_int64_t pcs_halt_r27; /* 110: halt procedure value */
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#define PCS_HALT_RESERVED 0
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#define PCS_HALT_POWERUP 1
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#define PCS_HALT_CONSOLE_HALT 2
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#define PCS_HALT_CONSOLE_CRASH 3
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#define PCS_HALT_KERNEL_MODE 4
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#define PCS_HALT_KERNEL_STACK_INVALID 5
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#define PCS_HALT_DOUBLE_ERROR_ABORT 6
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#define PCS_HALT_SCBB 7
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#define PCS_HALT_PTBR 8 /* 9-FF: reserved */
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u_int64_t pcs_halt_reason; /* 118: */
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u_int64_t pcs_reserved_soft; /* 120: preserved software */
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u_int64_t pcs_buffer[21]; /* 128: console buffers */
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#define PALvar_reserved 0
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#define PALvar_OpenVMS 1
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#define PALvar_OSF1 2
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u_int64_t pcs_palrevisions[16]; /* 1D0: PALcode revisions */
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u_int64_t pcs_reserved_arch[6]; /* 250: reserved arch */
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};
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/*
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* CTB: Console Terminal Block
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*/
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struct ctb {
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u_int64_t ctb_type; /* 0: always 4 */
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u_int64_t ctb_unit; /* 8: */
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u_int64_t ctb_reserved; /* 16: */
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u_int64_t ctb_len; /* 24: bytes of info */
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u_int64_t ctb_ipl; /* 32: console ipl level */
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vm_offset_t ctb_tintr_vec; /* 40: transmit vec (0x800) */
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vm_offset_t ctb_rintr_vec; /* 48: receive vec (0x800) */
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#define CTB_GRAPHICS 3 /* graphics device */
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#define CTB_NETWORK 0xC0 /* network device */
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#define CTB_PRINTERPORT 2 /* printer port on the SCC */
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u_int64_t ctb_term_type; /* 56: terminal type */
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u_int64_t ctb_keybd_type; /* 64: keyboard nationality */
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vm_offset_t ctb_keybd_trans; /* 72: trans. table addr */
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vm_offset_t ctb_keybd_map; /* 80: map table addr */
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u_int64_t ctb_keybd_state; /* 88: keyboard flags */
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u_int64_t ctb_keybd_last; /* 96: last key entered */
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vm_offset_t ctb_font_us; /* 104: US font table addr */
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vm_offset_t ctb_font_mcs; /* 112: MCS font table addr */
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u_int64_t ctb_font_width; /* 120: font width, height */
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u_int64_t ctb_font_height; /* 128: in pixels */
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u_int64_t ctb_mon_width; /* 136: monitor width, height */
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u_int64_t ctb_mon_height; /* 144: in pixels */
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u_int64_t ctb_dpi; /* 152: monitor dots per inch */
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u_int64_t ctb_planes; /* 160: # of planes */
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u_int64_t ctb_cur_width; /* 168: cursor width, height */
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u_int64_t ctb_cur_height; /* 176: in pixels */
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u_int64_t ctb_head_cnt; /* 184: # of heads */
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u_int64_t ctb_opwindow; /* 192: opwindow on screen */
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vm_offset_t ctb_head_offset; /* 200: offset to head info */
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vm_offset_t ctb_putchar; /* 208: output char to TURBO */
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u_int64_t ctb_io_state; /* 216: I/O flags */
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u_int64_t ctb_listen_state; /* 224: listener flags */
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vm_offset_t ctb_xaddr; /* 232: extended info addr */
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u_int64_t ctb_turboslot; /* 248: TURBOchannel slot # */
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u_int64_t ctb_server_off; /* 256: offset to server info */
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u_int64_t ctb_line_off; /* 264: line parameter offset */
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u_int8_t ctb_csd; /* 272: console specific data */
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};
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/*
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* CRD: Console Routine Descriptor
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*/
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struct crd {
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int64_t descriptor;
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int (*code)();
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};
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/*
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* CRB: Console Routine Block
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*/
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struct crb {
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struct crd *crb_v_dispatch; /* 0: virtual dispatch addr */
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vm_offset_t crb_p_dispatch; /* 8: phys dispatch addr */
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struct crd *crb_v_fixup; /* 10: virtual fixup addr */
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vm_offset_t crb_p_fixup; /* 18: phys fixup addr */
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u_int64_t crb_map_cnt; /* 20: phys/virt map entries */
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u_int64_t crb_page_cnt; /* 28: pages to be mapped */
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};
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/*
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* MDDT: Memory Data Descriptor Table
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*/
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struct mddt {
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int64_t mddt_cksum; /* 0: 7-N checksum */
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vm_offset_t mddt_physaddr; /* 8: bank config addr
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* IMPLEMENTATION SPECIFIC
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*/
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u_int64_t mddt_cluster_cnt; /* 10: memory cluster count */
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struct {
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vm_offset_t mddt_pfn; /* 0: starting PFN */
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u_int64_t mddt_pg_cnt; /* 8: 8KB page count */
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u_int64_t mddt_pg_test; /* 10: tested page count */
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vm_offset_t mddt_v_bitaddr; /* 18: bitmap virt addr */
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vm_offset_t mddt_p_bitaddr; /* 20: bitmap phys addr */
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int64_t mddt_bit_cksum; /* 28: bitmap checksum */
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#define MDDT_PALCODE 0x01 /* console and PAL only */
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#define MDDT_SYSTEM 0x00 /* system software only */
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#define MDDT_mbz 0xfffffffffffffffe /* 1:63 -- must be zero */
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int64_t mddt_usage; /* 30: bitmap permissions */
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} mddt_clusters[1]; /* variable length array */
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};
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#endif /* ASSEMBLER */
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