79 lines
2.9 KiB
C
79 lines
2.9 KiB
C
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/* $NetBSD: plumpowerreg.h,v 1.1 1999/11/21 06:50:26 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* POWER CONTROLLER
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*/
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#define PLUM_POWER_REGBASE 0x7000
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#define PLUM_POWER_REGSIZE 0x1000
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/* power control register */
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#define PLUM_POWER_PWRCONT_REG 0x000
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#define PLUM_POWER_PWRCONT_USBEN 0x00000400
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#define PLUM_POWER_PWRCONT_IO5OE 0x00000200
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#define PLUM_POWER_PWRCONT_LCDOE 0x00000100
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#define PLUM_POWER_PWRCONT_EXTPW2 0x00000040
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#define PLUM_POWER_PWRCONT_EXTPW1 0x00000020
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#define PLUM_POWER_PWRCONT_EXTPW0 0x00000010
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#define PLUM_POWER_PWRCONT_IO5PWR 0x00000008
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#define PLUM_POWER_PWRCONT_BKLIGHT 0x00000004
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#define PLUM_POWER_PWRCONT_LCDPWR 0x00000002
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#define PLUM_POWER_PWRCONT_LCDDSP 0x00000001
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/* clock control register */
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#define PLUM_POWER_CLKCONT_REG 0x004
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#define PLUM_POWER_CLKCONT_USBCLK2 0x00000020
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#define PLUM_POWER_CLKCONT_USBCLK1 0x00000010
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#define PLUM_POWER_CLKCONT_IO5CLK 0x00000008
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#define PLUM_POWER_CLKCONT_SMCLK 0x00000004
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#define PLUM_POWER_CLKCONT_PCCCLK2 0x00000002
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#define PLUM_POWER_CLKCONT_PCCCLK1 0x00000001
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/* mask rom control register */
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#define PLUM_POWER_MROMCNT_REG 0x008
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#define PLUM_POWER_MROMCNT_MROMSL1 0x00000004
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#define PLUM_POWER_MROMCNT_MROMSL0 0x00000002
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#define PLUM_POWER_MROMCNT_MRMAEN 0x00000001
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#define PLUM_POWER_MROMCNT_MROM_8MB 0x0
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#define PLUM_POWER_MROMCNT_MROM_4MB 0x1
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#define PLUM_POWER_MROMCNT_MROM_16MB 0x2
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/* input signal enable register (MCS access) */
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#define PLUM_POWER_INPENA_REG 0x00c
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#define PLUM_POWER_INPENA 0x00000001
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/* reset control register (I/O bus)*/
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#define PLUM_POWER_RESETC_REG 0x010
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#define PLUM_POWER_RESETC_IO5CL1 0x00000002
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#define PLUM_POWER_RESETC_IO5CL0 0x00000001
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#define PLUM_POWER_TESTMD_REG 0x100
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