2000-04-22 19:00:41 +04:00
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/* $NetBSD: via82c586reg.h,v 1.2 2000/04/22 15:00:41 uch Exp $ */
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1999-11-17 04:21:20 +03:00
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Register definitions for the VIA 82c586 PCI-ISA bridge interrupt controller.
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*/
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#define VP3_CFG_PIRQ_REG 0x54 /* PCI configuration space */
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#define VP3_CFG_KBDMISCCTRL12_REG 0x44
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#define VP3_CFG_IDEMISCCTRL3_REG 0x48
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#define VP3_CFG_MISCCTRL2_SHIFT 24
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#define VP3_CFG_MISCCTRL2_MASK 0x0f
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#define VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE 0x20
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#define VP3_CFG_MISCCTRL2_REG(reg) \
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(((reg) >> VP3_CFG_MISCCTRL2_SHIFT) & VP3_CFG_MISCCTRL2_MASK)
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#define VP3_CFG_TRIGGER_LEVEL 0
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#define VP3_CFG_TRIGGER_EDGE 1
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#define VP3_CFG_TRIGGER_MASK 0x01
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#define VP3_CFG_TRIGGER_SHIFT_PIRQA 3
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#define VP3_CFG_TRIGGER_SHIFT_PIRQB 2
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#define VP3_CFG_TRIGGER_SHIFT_PIRQC 1
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#define VP3_CFG_TRIGGER_SHIFT_PIRQD 0
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2000-04-22 19:00:41 +04:00
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#define VP3_CFG_INTR_MASK 0x0f
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1999-11-17 04:21:20 +03:00
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#define VP3_PIRQ_MASK 0xdefa
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#define VP3_CFG_INTR_SHIFT_PIRQA 0x14
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#define VP3_CFG_INTR_SHIFT_PIRQB 0x10
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#define VP3_CFG_INTR_SHIFT_PIRQC 0x1c
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#define VP3_CFG_INTR_SHIFT_PIRQD 0x0c
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#define VP3_PIRQ_NONE 0
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#define VP3_LEGAL_LINK(link) ((link) >= 0 && (link) <= 3)
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#define VP3_LEGAL_IRQ(irq) ((irq) >= 0 && (irq) <= 15 && \
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((1 << (irq)) & VP3_PIRQ_MASK) != 0)
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