1993-05-13 17:56:20 +04:00
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory and the Systems
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* Programming Group of the University of Utah Computer Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: scsi.c 1.3 90/01/27$
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*
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1993-05-22 11:56:12 +04:00
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* from: @(#)scsi.c 7.4 (Berkeley) 5/7/91
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* $Id: scsi.c,v 1.2 1993/05/22 07:59:21 cgd Exp $
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1993-05-13 17:56:20 +04:00
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*/
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/*
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* SCSI bus driver for standalone programs.
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*/
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#include <sys/param.h>
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#include <sys/reboot.h>
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#include "../dev/device.h"
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#include "../dev/scsireg.h"
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#include "scsivar.h"
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#include "saio.h"
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#include "samachdep.h"
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struct scsi_softc scsi_softc[NSCSI];
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#define scsiunit(x) ((x) >> 3)
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#define scsislave(x) ((x) & 7)
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void scsireset();
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int scsi_cmd_wait = 500;
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int scsi_data_wait = 300000;
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scsiinit()
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{
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extern struct hp_hw sc_table[];
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register struct hp_hw *hw;
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register struct scsi_softc *hs;
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register int i, addr;
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static int first = 1;
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i = 0;
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for (hw = sc_table; i < NSCSI && hw < &sc_table[MAXCTLRS]; hw++) {
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if (!HW_ISSCSI(hw))
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continue;
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hs = &scsi_softc[i];
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hs->sc_addr = hw->hw_kva;
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scsireset(i);
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if (howto & RB_ASKNAME)
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printf("scsi%d at sc%d\n", i, hw->hw_sc);
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/*
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* Adjust devtype on first call. This routine assumes that
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* adaptor is in the high byte of devtype.
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*/
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if (first && ((devtype >> 24) & 0xff) == hw->hw_sc) {
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devtype = (devtype & 0x00ffffff) | (i << 24);
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first = 0;
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}
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hs->sc_alive = 1;
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i++;
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}
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}
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scsialive(unit)
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register int unit;
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{
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unit = scsiunit(unit);
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if (unit >= NSCSI || scsi_softc[unit].sc_alive == 0)
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return (0);
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return (1);
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}
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void
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scsireset(unit)
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register int unit;
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{
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volatile register struct scsidevice *hd;
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register struct scsi_softc *hs;
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u_int i;
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unit = scsiunit(unit);
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hs = &scsi_softc[unit];
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hd = (struct scsidevice *)hs->sc_addr;
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hd->scsi_id = 0xFF;
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DELAY(100);
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/*
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* Disable interrupts then reset the FUJI chip.
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*/
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hd->scsi_csr = 0;
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hd->scsi_sctl = SCTL_DISABLE | SCTL_CTRLRST;
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hd->scsi_scmd = 0;
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hd->scsi_tmod = 0;
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hd->scsi_pctl = 0;
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hd->scsi_temp = 0;
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hd->scsi_tch = 0;
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hd->scsi_tcm = 0;
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hd->scsi_tcl = 0;
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hd->scsi_ints = 0;
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/*
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* Configure the FUJI chip with its SCSI address, all
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* interrupts enabled & appropriate parity.
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*/
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i = (~hd->scsi_hconf) & 0x7;
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hs->sc_scsi_addr = 1 << i;
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hd->scsi_bdid = i;
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if (hd->scsi_hconf & HCONF_PARITY)
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hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
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SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
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SCTL_INTR_ENAB | SCTL_PARITY_ENAB;
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else
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hd->scsi_sctl = SCTL_DISABLE | SCTL_ABRT_ENAB |
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SCTL_SEL_ENAB | SCTL_RESEL_ENAB |
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SCTL_INTR_ENAB;
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hd->scsi_sctl &=~ SCTL_DISABLE;
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}
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int
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scsiabort(hs, hd)
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register struct scsi_softc *hs;
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volatile register struct scsidevice *hd;
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{
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printf("scsi error: scsiabort\n");
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return (0);
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}
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static int
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issue_select(hd, target, our_addr)
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volatile register struct scsidevice *hd;
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u_char target, our_addr;
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{
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if (hd->scsi_ssts & (SSTS_INITIATOR|SSTS_TARGET|SSTS_BUSY))
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return (1);
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if (hd->scsi_ints & INTS_DISCON)
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hd->scsi_ints = INTS_DISCON;
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hd->scsi_pctl = 0;
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hd->scsi_temp = (1 << target) | our_addr;
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/* select timeout is hardcoded to 2ms */
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hd->scsi_tch = 0;
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hd->scsi_tcm = 32;
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hd->scsi_tcl = 4;
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hd->scsi_scmd = SCMD_SELECT;
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return (0);
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}
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static int
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wait_for_select(hd)
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volatile register struct scsidevice *hd;
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{
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u_char ints;
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while ((ints = hd->scsi_ints) == 0)
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DELAY(1);
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hd->scsi_ints = ints;
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return (!(hd->scsi_ssts & SSTS_INITIATOR));
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}
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static int
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ixfer_start(hd, len, phase, wait)
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volatile register struct scsidevice *hd;
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int len;
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u_char phase;
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register int wait;
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{
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hd->scsi_tch = len >> 16;
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hd->scsi_tcm = len >> 8;
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hd->scsi_tcl = len;
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hd->scsi_pctl = phase;
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hd->scsi_tmod = 0; /*XXX*/
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hd->scsi_scmd = SCMD_XFR | SCMD_PROG_XFR;
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/* wait for xfer to start or svc_req interrupt */
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while ((hd->scsi_ssts & SSTS_BUSY) == 0) {
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if (hd->scsi_ints || --wait < 0)
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return (0);
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DELAY(1);
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}
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return (1);
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}
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static int
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ixfer_out(hd, len, buf)
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volatile register struct scsidevice *hd;
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int len;
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register u_char *buf;
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{
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register int wait = scsi_data_wait;
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for (; len > 0; --len) {
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while (hd->scsi_ssts & SSTS_DREG_FULL) {
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if (hd->scsi_ints || --wait < 0)
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return (len);
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DELAY(1);
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}
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hd->scsi_dreg = *buf++;
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}
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return (0);
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}
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static int
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ixfer_in(hd, len, buf)
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volatile register struct scsidevice *hd;
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int len;
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register u_char *buf;
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{
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register int wait = scsi_data_wait;
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for (; len > 0; --len) {
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while (hd->scsi_ssts & SSTS_DREG_EMPTY) {
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if (hd->scsi_ints || --wait < 0) {
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while (! (hd->scsi_ssts & SSTS_DREG_EMPTY)) {
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*buf++ = hd->scsi_dreg;
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--len;
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}
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return (len);
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}
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DELAY(1);
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}
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*buf++ = hd->scsi_dreg;
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}
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return (len);
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}
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static int
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scsiicmd(hs, target, cbuf, clen, buf, len, xferphase)
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struct scsi_softc *hs;
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int target;
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u_char *cbuf;
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int clen;
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u_char *buf;
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int len;
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u_char xferphase;
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{
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volatile register struct scsidevice *hd =
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(struct scsidevice *)hs->sc_addr;
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int i;
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u_char phase, ints;
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register int wait;
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/* select the SCSI bus (it's an error if bus isn't free) */
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if (issue_select(hd, target, hs->sc_scsi_addr))
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return (0);
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if (wait_for_select(hd))
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return (0);
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/*
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* Wait for a phase change (or error) then let the device
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* sequence us through the various SCSI phases.
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*/
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phase = CMD_PHASE;
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while (1) {
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wait = scsi_cmd_wait;
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switch (phase) {
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case CMD_PHASE:
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if (ixfer_start(hd, clen, phase, wait))
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if (ixfer_out(hd, clen, cbuf))
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goto abort;
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phase = xferphase;
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break;
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case DATA_IN_PHASE:
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if (len <= 0)
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goto abort;
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wait = scsi_data_wait;
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if (ixfer_start(hd, len, phase, wait) ||
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!(hd->scsi_ssts & SSTS_DREG_EMPTY))
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ixfer_in(hd, len, buf);
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phase = STATUS_PHASE;
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break;
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case DATA_OUT_PHASE:
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if (len <= 0)
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goto abort;
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wait = scsi_data_wait;
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if (ixfer_start(hd, len, phase, wait))
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if (ixfer_out(hd, len, buf))
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goto abort;
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phase = STATUS_PHASE;
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break;
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case STATUS_PHASE:
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wait = scsi_data_wait;
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if (ixfer_start(hd, sizeof(hs->sc_stat), phase, wait) ||
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!(hd->scsi_ssts & SSTS_DREG_EMPTY))
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ixfer_in(hd, sizeof(hs->sc_stat), &hs->sc_stat);
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phase = MESG_IN_PHASE;
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break;
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case MESG_IN_PHASE:
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if (ixfer_start(hd, sizeof(hs->sc_msg), phase, wait) ||
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!(hd->scsi_ssts & SSTS_DREG_EMPTY)) {
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ixfer_in(hd, sizeof(hs->sc_msg), &hs->sc_msg);
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hd->scsi_scmd = SCMD_RST_ACK;
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}
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phase = BUS_FREE_PHASE;
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break;
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case BUS_FREE_PHASE:
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return (1);
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default:
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printf("unexpected scsi phase %d\n", phase);
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goto abort;
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}
|
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|
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/* wait for last command to complete */
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while ((ints = hd->scsi_ints) == 0) {
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if (--wait < 0)
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goto abort;
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DELAY(1);
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}
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hd->scsi_ints = ints;
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if (ints & INTS_SRV_REQ)
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phase = hd->scsi_psns & PHASE;
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else if (ints & INTS_DISCON)
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return (1);
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else if ((ints & INTS_CMD_DONE) == 0) {
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goto abort;
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}
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}
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abort:
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|
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scsiabort(hs, hd);
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return (0);
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}
|
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|
|
int
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|
|
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scsi_test_unit_rdy(unit)
|
|
|
|
{
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|
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int ctlr = scsiunit(unit);
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|
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int slave = scsislave(unit);
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|
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register struct scsi_softc *hs = &scsi_softc[ctlr];
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|
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static struct scsi_cdb6 cdb = { CMD_TEST_UNIT_READY };
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if (scsiicmd(hs, slave, &cdb, sizeof(cdb), (u_char *)0, 0,
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STATUS_PHASE) == 0)
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return (0);
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return (hs->sc_stat == 0);
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|
|
}
|
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|
|
|
|
|
int
|
|
|
|
scsi_request_sense(unit, buf, len)
|
|
|
|
int unit;
|
|
|
|
u_char *buf;
|
|
|
|
unsigned len;
|
|
|
|
{
|
|
|
|
int ctlr = scsiunit(unit);
|
|
|
|
int slave = scsislave(unit);
|
|
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
|
|
static struct scsi_cdb6 cdb = { CMD_REQUEST_SENSE };
|
|
|
|
|
|
|
|
cdb.len = len;
|
|
|
|
return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE));
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
scsi_read_capacity(unit, buf, len)
|
|
|
|
int unit;
|
|
|
|
u_char *buf;
|
|
|
|
unsigned len;
|
|
|
|
{
|
|
|
|
int ctlr = scsiunit(unit);
|
|
|
|
int slave = scsislave(unit);
|
|
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
|
|
static struct scsi_cdb10 cdb = { CMD_READ_CAPACITY };
|
|
|
|
|
|
|
|
return (scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE));
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
scsi_tt_read(unit, buf, len, blk, nblk)
|
|
|
|
int unit;
|
|
|
|
u_char *buf;
|
|
|
|
u_int len;
|
|
|
|
daddr_t blk;
|
|
|
|
u_int nblk;
|
|
|
|
{
|
|
|
|
int ctlr = scsiunit(unit);
|
|
|
|
int slave = scsislave(unit);
|
|
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
|
|
struct scsi_cdb10 cdb;
|
|
|
|
int stat;
|
|
|
|
|
|
|
|
bzero(&cdb, sizeof(cdb));
|
|
|
|
cdb.cmd = CMD_READ_EXT;
|
|
|
|
cdb.lbah = blk >> 24;
|
|
|
|
cdb.lbahm = blk >> 16;
|
|
|
|
cdb.lbalm = blk >> 8;
|
|
|
|
cdb.lbal = blk;
|
|
|
|
cdb.lenh = nblk >> (8 + DEV_BSHIFT);
|
|
|
|
cdb.lenl = nblk >> DEV_BSHIFT;
|
|
|
|
stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_IN_PHASE);
|
|
|
|
if (stat == 0)
|
|
|
|
return (1);
|
|
|
|
return (hs->sc_stat);
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
scsi_tt_write(unit, buf, len, blk, nblk)
|
|
|
|
int unit;
|
|
|
|
u_char *buf;
|
|
|
|
u_int len;
|
|
|
|
daddr_t blk;
|
|
|
|
u_int nblk;
|
|
|
|
{
|
|
|
|
int ctlr = scsiunit(unit);
|
|
|
|
int slave = scsislave(unit);
|
|
|
|
register struct scsi_softc *hs = &scsi_softc[ctlr];
|
|
|
|
struct scsi_cdb10 cdb;
|
|
|
|
int stat;
|
|
|
|
|
|
|
|
bzero(&cdb, sizeof(cdb));
|
|
|
|
cdb.cmd = CMD_WRITE_EXT;
|
|
|
|
cdb.lbah = blk >> 24;
|
|
|
|
cdb.lbahm = blk >> 16;
|
|
|
|
cdb.lbalm = blk >> 8;
|
|
|
|
cdb.lbal = blk;
|
|
|
|
cdb.lenh = nblk >> (8 + DEV_BSHIFT);
|
|
|
|
cdb.lenl = nblk >> DEV_BSHIFT;
|
|
|
|
stat = scsiicmd(hs, slave, &cdb, sizeof(cdb), buf, len, DATA_OUT_PHASE);
|
|
|
|
if (stat == 0)
|
|
|
|
return (1);
|
|
|
|
return (hs->sc_stat);
|
|
|
|
}
|