77 lines
2.9 KiB
C
77 lines
2.9 KiB
C
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/* $NetBSD: simidereg.h,v 1.1 1997/10/14 23:20:57 mark Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe
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* Copyright (c) 1997 Causality Limited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Thanks to Gareth Simpson, Simtec Electronics for providing
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* the hardware information.
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*/
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/*
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* Registers and address offsets for the Simtec IDE card.
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*/
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/* IDE drive registers */
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#define PRIMARY_DRIVE_REGISTERS_POFFSET 0x0000
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#define PRIMARY_AUX_REGISTER_POFFSET 0x0700
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#define SECONDARY_DRIVE_REGISTERS_POFFSET 0x1000
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#define SECONDARY_AUX_REGISTER_POFFSET 0x1700
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#define DRIVE_REGISTERS_SPACE 0x800
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#define DRIVE_REGISTER_BYTE_SPACING 128
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/* Other registers */
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#define CONTROL_REGISTERS_POFFSET 0x2000
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#define CONTROL_REGISTER_SPACE 8
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#define CONTROL_REGISTER_OFFSET 0
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#define CONTROL_RESET 0x80
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#define CONTROL_IORDY 0x40
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#define CONTROL_8_BIT 0x20
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#define CONTROL_IDE_ENABLE 0x10
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#define CONTROL_SLOW_MODE 0x08
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#define CONTROL_ROM_WRITE 0x04
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#define CONTROL_SECONDARY_IRQ 0x02
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#define CONTROL_PRIMARY_IRQ 0x01
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#define STATUS_REGISTER_OFFSET 1
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#define STATUS_RESET 0x80
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#define STATUS_IORDY 0x40
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#define STATUS_ADDR_TEST 0x20
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#define STATUS_CS_TEST 0x10
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#define STATUS_RW_TEST 0x08
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#define STATUS_IRQ 0x01
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#define STATUS_FAULT (STATUS_ADDR_TEST | STATUS_CS_TEST \
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| STATUS_RW_TEST | STATUS_RESET)
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