161 lines
5.3 KiB
C
161 lines
5.3 KiB
C
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/* $NetBSD: tx39uartreg.h,v 1.1 1999/11/20 19:56:38 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Toshiba TX3912/3922 UART module
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*/
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#define TX39_UARTACTRL1_REG 0x0b0
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#define TX39_UARTACTRL2_REG 0x0b4
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#define TX39_UARTADMACTRL1_REG 0x0b8
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#define TX39_UARTADMACTRL2_REG 0x0bc
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#define TX39_UARTADMACNT_REG 0x0c0
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#define TX39_UARTATXHOLD_REG 0x0c4
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#define TX39_UARTARXHOLD_REG 0x0c4
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#define TX39_UARTBCTRL1_REG 0x0c8
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#define TX39_UARTBCTRL2_REG 0x0cc
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#define TX39_UARTBDMACTRL1_REG 0x0d0
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#define TX39_UARTBDMACTRL2_REG 0x0d4
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#define TX39_UARTBDMACNT_REG 0x0d8
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#define TX39_UARTBTXHOLD_REG 0x0dc
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#define TX39_UARTBRXHOLD_REG 0x0dc
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#define TX39_UARTA_REG_START 0x0b0
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#define TX39_UARTB_REG_START 0x0c8
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#define TX39_UARTCTRL1_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START))
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#define TX39_UARTCTRL2_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 4)
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#define TX39_UARTDMACTRL1_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 8)
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#define TX39_UARTDMACTRL2_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 12)
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#define TX39_UARTDMACNT_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 16)
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#define TX39_UARTTXHOLD_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20)
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#define TX39_UARTRXHOLD_REG(x) \
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(((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20)
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/*
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* UART Control 1 Register
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*/
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/* R */
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#define TX39_UARTCTRL1_UARTON 0x80000000
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#define TX39_UARTCTRL1_EMPTY 0x40000000
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#define TX39_UARTCTRL1_PRXHOLDFULL 0x20000000
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#define TX39_UARTCTRL1_RXHOLDFULL 0x10000000
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/* R/W */
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#define TX39_UARTCTRL1_ENDMARX 0x00008000
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#define TX39_UARTCTRL1_ENDMATX 0x00004000
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#define TX39_UARTCTRL1_TESTMODE 0x00002000
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#define TX39_UARTCTRL1_ENBREAHALT 0x00001000
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#define TX39_UARTCTRL1_ENDMATEST 0x00000800
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#define TX39_UARTCTRL1_ENDMALOOP 0x00000400
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#define TX39_UARTCTRL1_PULSEOPT2 0x00000200
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#define TX39_UARTCTRL1_PULSEOPT1 0x00000100
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#define TX39_UARTCTRL1_DTINVERT 0x00000080
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#define TX39_UARTCTRL1_DISTXD 0x00000040
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#define TX39_UARTCTRL1_TWOSTOP 0x00000020
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#define TX39_UARTCTRL1_LOOPBACK 0x00000010
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#define TX39_UARTCTRL1_BIT7 0x00000008
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#define TX39_UARTCTRL1_EVENPARITY 0x00000004
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#define TX39_UARTCTRL1_ENPARITY 0x00000002
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#define TX39_UARTCTRL1_ENUART 0x00000001
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/*
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* UART Control 2 Register
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*/
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/* W */
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/*
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* BaudRate = UART Clock Hz / ((BAUDRATE + 1) * 16)
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*/
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#define TX3922_UARTCLOCKHZ 9216000
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#define TX3912_UARTCLOCKHZ 3686400
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#define TX39_UARTCTRL2_BAUDRATE_SHIFT 0
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#define TX3912_UARTCTRL2_BAUDRATE_MASK 0x3ff
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#define TX3922_UARTCTRL2_BAUDRATE_MASK 0x7ff
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#ifdef TX391X
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#define TX39_UARTCLOCKHZ TX3912_UARTCLOCKHZ
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#define TX39_UARTCTRL2_BAUDRATE_MASK TX3912_UARTCTRL2_BAUDRATE_MASK
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#elif defined TX392X
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#define TX39_UARTCLOCKHZ TX3922_UARTCLOCKHZ
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#define TX39_UARTCTRL2_BAUDRATE_MASK TX3922_UARTCTRL2_BAUDRATE_MASK
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#endif
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#define TX39_UARTCTRL2_BAUDRATE_SET(cr, val) \
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((cr) | (((val) << TX39_UARTCTRL2_BAUDRATE_SHIFT) & \
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(TX39_UARTCTRL2_BAUDRATE_MASK << TX39_UARTCTRL2_BAUDRATE_SHIFT)))
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/*
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* UART DMA Control 1 Register
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*/
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/* W */
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#define TX39_UARTDMACTRL1_DMASTARTVAL_MASK 0xfffffffc
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#define TX39_UARTDMACTRL1_DMASTARTVAL_SET(cr, val) \
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((cr) | ((val) & TX39_UARTDMACTRL1_DMASTARTVAL_MASK))
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/*
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* UART DMA Control 2 Register
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*/
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/* W */
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#define TX39_UARTDMACTRL2_DMALENGTH_MASK 0x0000ffff
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#define TX39_UARTDMACTRL2_DMALENGTH_SET(cr, val) \
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((cr) | ((val) & TX39_UARTDMACTRL1_DMALENGTH_MASK))
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/*
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* UART DMA Count Register
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*/
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/* R */
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#define TX39_UARTDMACNT_DMACNT_SHIFT 0
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#define TX39_UARTDMACNT_DMACNT_MASK 0xffff
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#define TX39_UARTDMACNT_DMACNT(cr) \
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((cr) & TX39_UARTDMACNT_DMACNT_MASK)
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/*
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* UART Transmit Holding Register
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*/
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/* W */
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#define TX39_UARTTXHOLD_BREAK 0x00000100
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#define TX39_UARTTXHOLD_TXDATA_SHIFT 0
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#define TX39_UARTTXHOLD_TXDATA_MASK 0x000000ff
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#define TX39_UARTTXHOLD_TXDATA_SET(cr, val) \
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((cr) | ((val) & TX39_UARTTXHOLD_TXDATA_MASK))
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/*
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* UART Receiver Holding Register
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*/
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/* R */
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#define TX39_UARTRXHOLD_RXDATA_SHIFT 0
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#define TX39_UARTRXHOLD_RXDATA_MASK 0x000000ff
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#define TX39_UARTRXHOLD_RXDATA(cr) \
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((cr) & TX39_UARTRXHOLD_RXDATA_MASK)
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