385 lines
18 KiB
C
385 lines
18 KiB
C
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/* $NetBSD: qereg.h,v 1.1 1999/01/17 20:44:18 pk Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1998 Jason L. Wright.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* QE Channel registers
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*-
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struct qe_cregs {
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u_int32_t ctrl; // control
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u_int32_t stat; // status
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u_int32_t rxds; // rx descriptor ring ptr
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u_int32_t txds; // tx descriptor ring ptr
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u_int32_t rimask; // rx interrupt mask
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u_int32_t timask; // tx interrupt mask
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u_int32_t qmask; // qec error interrupt mask
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u_int32_t mmask; // mace error interrupt mask
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u_int32_t rxwbufptr; // local memory rx write ptr
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u_int32_t rxrbufptr; // local memory rx read ptr
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u_int32_t txwbufptr; // local memory tx write ptr
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u_int32_t txrbufptr; // local memory tx read ptr
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u_int32_t ccnt; // collision counter
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u_int32_t pipg; // inter-frame gap
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};
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* register indices: */
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#define QE_CRI_CTRL (0*4)
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#define QE_CRI_STAT (1*4)
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#define QE_CRI_RXDS (2*4)
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#define QE_CRI_TXDS (3*4)
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#define QE_CRI_RIMASK (4*4)
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#define QE_CRI_TIMASK (5*4)
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#define QE_CRI_QMASK (6*4)
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#define QE_CRI_MMASK (7*4)
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#define QE_CRI_RXWBUF (8*4)
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#define QE_CRI_RXRBUF (9*4)
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#define QE_CRI_TXWBUF (10*4)
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#define QE_CRI_TXRBUF (11*4)
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#define QE_CRI_CCNT (12*4)
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#define QE_CRI_PIPG (13*4)
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/* qe_cregs.ctrl: control. */
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#define QE_CR_CTRL_RXOFF 0x00000004 /* disable receiver */
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#define QE_CR_CTRL_RESET 0x00000002 /* reset this channel */
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#define QE_CR_CTRL_TWAKEUP 0x00000001 /* tx dma wakeup */
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/* qe_cregs.stat: status. */
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#define QE_CR_STAT_EDEFER 0x10000000 /* excessive defers */
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#define QE_CR_STAT_CLOSS 0x08000000 /* loss of carrier */
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#define QE_CR_STAT_ERETRIES 0x04000000 /* >16 retries */
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#define QE_CR_STAT_LCOLL 0x02000000 /* late tx collision */
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#define QE_CR_STAT_FUFLOW 0x01000000 /* fifo underflow */
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#define QE_CR_STAT_JERROR 0x00800000 /* jabber error */
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#define QE_CR_STAT_BERROR 0x00400000 /* babble error */
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#define QE_CR_STAT_TXIRQ 0x00200000 /* tx interrupt */
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#define QE_CR_STAT_TCCOFLOW 0x00100000 /* tx collision cntr expired */
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#define QE_CR_STAT_TXDERROR 0x00080000 /* tx descriptor is bad */
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#define QE_CR_STAT_TXLERR 0x00040000 /* tx late error */
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#define QE_CR_STAT_TXPERR 0x00020000 /* tx parity error */
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#define QE_CR_STAT_TXSERR 0x00010000 /* tx sbus error ack */
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#define QE_CR_STAT_RCCOFLOW 0x00001000 /* rx collision cntr expired */
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#define QE_CR_STAT_RUOFLOW 0x00000800 /* rx runt counter expired */
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#define QE_CR_STAT_MCOFLOW 0x00000400 /* rx missed counter expired */
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#define QE_CR_STAT_RXFOFLOW 0x00000200 /* rx fifo over flow */
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#define QE_CR_STAT_RLCOLL 0x00000100 /* rx late collision */
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#define QE_CR_STAT_FCOFLOW 0x00000080 /* rx frame counter expired */
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#define QE_CR_STAT_CECOFLOW 0x00000040 /* rx crc error cntr expired */
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#define QE_CR_STAT_RXIRQ 0x00000020 /* rx interrupt */
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#define QE_CR_STAT_RXDROP 0x00000010 /* rx dropped packet */
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#define QE_CR_STAT_RXSMALL 0x00000008 /* rx buffer too small */
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#define QE_CR_STAT_RXLERR 0x00000004 /* rx late error */
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#define QE_CR_STAT_RXPERR 0x00000002 /* rx parity error */
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#define QE_CR_STAT_RXSERR 0x00000001 /* rx sbus error ack */
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#define QE_CR_STAT_BITS "\177\020" \
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"b\0RXSERR\0b\1RXPERR\0b\2RXLERR\0" \
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"b\3RXSMALL\0b\4RXDROP\0b\5RXIRQ\0" \
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"b\6CECOFLOW\0b\7FCOFLOW\0b\10RLCOLL\0" \
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"b\11RXFOFLOW\0b\12MCOFLOW\0b\13RUOFLOW\0" \
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"b\14RCCOFLOW\0b\15TXSERR\0b\16TXPERR\0" \
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"b\17TXLERR\0b\20TXDERROR\0b\21TCCOFLOW\0" \
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"b\22TXIRQ\0b\23BERROR\0b\24JERROR\0" \
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"b\25FUFLOW\0b\26LCOLL\0b\27ERETRIES\0" \
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"b\30CLOSS\0b\31EDEFER\0\0"
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/*
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* Errors: all status bits except for TX/RX IRQ
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*/
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#define QE_CR_STAT_ALLERRORS \
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( QE_CR_STAT_EDEFER | QE_CR_STAT_CLOSS | QE_CR_STAT_ERETRIES \
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| QE_CR_STAT_LCOLL | QE_CR_STAT_FUFLOW | QE_CR_STAT_JERROR \
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| QE_CR_STAT_BERROR | QE_CR_STAT_TCCOFLOW | QE_CR_STAT_TXDERROR \
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| QE_CR_STAT_TXLERR | QE_CR_STAT_TXPERR | QE_CR_STAT_TXSERR \
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| QE_CR_STAT_RCCOFLOW | QE_CR_STAT_RUOFLOW | QE_CR_STAT_MCOFLOW \
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| QE_CR_STAT_RXFOFLOW | QE_CR_STAT_RLCOLL | QE_CR_STAT_FCOFLOW \
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| QE_CR_STAT_CECOFLOW | QE_CR_STAT_RXDROP | QE_CR_STAT_RXSMALL \
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| QE_CR_STAT_RXLERR | QE_CR_STAT_RXPERR | QE_CR_STAT_RXSERR)
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/* qe_cregs.qmask: qec error interrupt mask. */
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#define QE_CR_QMASK_COFLOW 0x00100000 /* collision cntr overflow */
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#define QE_CR_QMASK_TXDERROR 0x00080000 /* tx descriptor error */
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#define QE_CR_QMASK_TXLERR 0x00040000 /* tx late error */
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#define QE_CR_QMASK_TXPERR 0x00020000 /* tx parity error */
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#define QE_CR_QMASK_TXSERR 0x00010000 /* tx sbus error ack */
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#define QE_CR_QMASK_RXDROP 0x00000010 /* rx packet dropped */
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#define QE_CR_QMASK_RXSMALL 0x00000008 /* rx buffer too small */
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#define QE_CR_QMASK_RXLERR 0x00000004 /* rx late error */
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#define QE_CR_QMASK_RXPERR 0x00000002 /* rx parity error */
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#define QE_CR_QMASK_RXSERR 0x00000001 /* rx sbus error ack */
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/* qe_cregs.mmask: MACE error interrupt mask. */
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#define QE_CR_MMASK_EDEFER 0x10000000 /* excess defer */
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#define QE_CR_MMASK_CLOSS 0x08000000 /* carrier loss */
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#define QE_CR_MMASK_ERETRY 0x04000000 /* excess retry */
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#define QE_CR_MMASK_LCOLL 0x02000000 /* late collision error */
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#define QE_CR_MMASK_UFLOW 0x01000000 /* underflow */
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#define QE_CR_MMASK_JABBER 0x00800000 /* jabber error */
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#define QE_CR_MMASK_BABBLE 0x00400000 /* babble error */
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#define QE_CR_MMASK_OFLOW 0x00000800 /* overflow */
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#define QE_CR_MMASK_RXCOLL 0x00000400 /* rx coll-cntr overflow */
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#define QE_CR_MMASK_RPKT 0x00000200 /* runt pkt overflow */
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#define QE_CR_MMASK_MPKT 0x00000100 /* missed pkt overflow */
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/* qe_cregs.pipg: inter-frame gap. */
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#define QE_CR_PIPG_TENAB 0x00000020 /* enable throttle */
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#define QE_CR_PIPG_MMODE 0x00000010 /* manual mode */
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#define QE_CR_PIPG_WMASK 0x0000000f /* sbus wait mask */
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/*
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* MACE registers
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*-
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struct qe_mregs {
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u_int8_t rcvfifo; [0] // receive fifo
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u_int8_t xmtfifo; [1] // transmit fifo
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u_int8_t xmtfc; [2] // transmit frame control
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u_int8_t xmtfs; [3] // transmit frame status
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u_int8_t xmtrc; [4] // tx retry count
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u_int8_t rcvfc; [5] // receive frame control
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u_int8_t rcvfs; [6] // receive frame status
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u_int8_t fifofc; [7] // fifo frame count
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u_int8_t ir; [8] // interrupt register
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u_int8_t imr; [9] // interrupt mask register
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u_int8_t pr; [10] // poll register
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u_int8_t biucc; [11] // biu config control
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u_int8_t fifocc; [12] // fifo config control
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u_int8_t maccc; [13] // mac config control
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u_int8_t plscc; [14] // pls config control
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u_int8_t phycc; [15] // phy config control
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u_int8_t chipid1; [16] // chipid, low byte
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u_int8_t chipid2; [17] // chipid, high byte
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u_int8_t iac; [18] // internal address config
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u_int8_t _reserved0; [19] // reserved
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u_int8_t ladrf; [20] // logical address filter
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u_int8_t padr; [21] // physical address
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u_int8_t _reserved1; [22] // reserved
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u_int8_t _reserved2; [23] // reserved
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u_int8_t mpc; [24] // missed packet count
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u_int8_t _reserved3; [25] // reserved
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u_int8_t rntpc; [26] // runt packet count
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u_int8_t rcvcc; [27] // receive collision count
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u_int8_t _reserved4; [28] // reserved
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u_int8_t utr; [29] // user test register
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u_int8_t rtr1; [30] // reserved test register 1
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u_int8_t rtr2; [31] // reserved test register 2
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};
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* register indices: */
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#define QE_MRI_RCVFIFO 0 // receive fifo
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#define QE_MRI_XMTFIFO 1 // transmit fifo
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#define QE_MRI_XMTFC 2 // transmit frame control
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#define QE_MRI_XMTFS 3 // transmit frame status
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#define QE_MRI_XMTRC 4 // tx retry count
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#define QE_MRI_RCVFC 5 // receive frame control
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#define QE_MRI_RCVFS 6 // receive frame status
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#define QE_MRI_FIFOFC 7 // fifo frame count
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#define QE_MRI_IR 8 // interrupt register
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#define QE_MRI_IMR 9 // interrupt mask register
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#define QE_MRI_PR 10 // poll register
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#define QE_MRI_BIUCC 11 // biu config control
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#define QE_MRI_FIFOCC 12 // fifo config control
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#define QE_MRI_MACCC 13 // mac config control
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#define QE_MRI_PLSCC 14 // pls config control
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#define QE_MRI_PHYCC 15 // phy config control
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#define QE_MRI_CHIPID1 16 // chipid, low byte
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#define QE_MRI_CHIPID2 17 // chipid, high byte
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#define QE_MRI_IAC 18 // internal address config
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#define QE_MRI_LADRF 20 // logical address filter
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#define QE_MRI_PADR 21 // physical address
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#define QE_MRI_MPC 24 // missed packet count
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#define QE_MRI_RNTPC 26 // runt packet count
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#define QE_MRI_RCVCC 27 // receive collision count
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#define QE_MRI_UTR 29 // user test register
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#define QE_MRI_RTR1 30 // reserved test register 1
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#define QE_MRI_RTR2 31 // reserved test register 2
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/* qe_mregs.xmtfc: transmit frame control. */
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#define QE_MR_XMTFC_DRETRY 0x80 /* disable retries */
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#define QE_MR_XMTFC_DXMTFCS 0x08 /* disable tx fcs */
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#define QE_MR_XMTFC_APADXMT 0x01 /* enable auto padding */
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/* qe_mregs.xmtfs: transmit frame status. */
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#define QE_MR_XMTFS_XMTSV 0x80 /* tx valid */
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#define QE_MR_XMTFS_UFLO 0x40 /* tx underflow */
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#define QE_MR_XMTFS_LCOL 0x20 /* tx late collision */
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#define QE_MR_XMTFS_MORE 0x10 /* tx > 1 retries */
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#define QE_MR_XMTFS_ONE 0x08 /* tx 1 retry */
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#define QE_MR_XMTFS_DEFER 0x04 /* tx pkt deferred */
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#define QE_MR_XMTFS_LCAR 0x02 /* tx carrier lost */
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#define QE_MR_XMTFS_RTRY 0x01 /* tx retry error */
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/* qe_mregs.xmtrc: transmit retry count. */
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#define QE_MR_XMTRC_EXDEF 0x80 /* tx excess defers */
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#define QE_MR_XMTRC_XMTRC 0x0f /* tx retry count mask */
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/* qe_mregs.rcvfc: receive frame control. */
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#define QE_MR_RCVFC_LLRCV 0x08 /* rx low latency */
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#define QE_MR_RCVFC_MR 0x04 /* rx addr match/reject */
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#define QE_MR_RCVFC_ASTRPRCV 0x01 /* rx auto strip */
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/* qe_mregs.rcvfs: receive frame status. */
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#define QE_MR_RCVFS_OFLO 0x80 /* rx overflow */
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#define QE_MR_RCVFS_CLSN 0x40 /* rx late collision */
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#define QE_MR_RCVFS_FRAM 0x20 /* rx framing error */
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#define QE_MR_RCVFS_FCS 0x10 /* rx fcs error */
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#define QE_MR_RCVFS_RCVCNT 0x0f /* rx msg byte count mask */
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/* qe_mregs.fifofc: fifo frame count. */
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#define QE_MR_FIFOFC_RCVFC 0xf0 /* rx fifo frame count */
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#define QE_MR_FIFOFC_XMTFC 0x0f /* tx fifo frame count */
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/* qe_mregs.ir: interrupt register. */
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#define QE_MR_IR_JAB 0x80 /* jabber error */
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#define QE_MR_IR_BABL 0x40 /* babble error */
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#define QE_MR_IR_CERR 0x20 /* collision error */
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#define QE_MR_IR_RCVCCO 0x10 /* collision cnt overflow */
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#define QE_MR_IR_RNTPCO 0x08 /* runt pkt cnt overflow */
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#define QE_MR_IR_MPCO 0x04 /* miss pkt cnt overflow */
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#define QE_MR_IR_RCVINT 0x02 /* packet received */
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#define QE_MR_IR_XMTINT 0x01 /* packet transmitted */
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/* qe_mregs.imr: interrupt mask register. */
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#define QE_MR_IMR_JABM 0x80 /* jabber errors */
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#define QE_MR_IMR_BABLM 0x40 /* babble errors */
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#define QE_MR_IMR_CERRM 0x20 /* collision errors */
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#define QE_MR_IMR_RCVCCOM 0x10 /* rx collision count oflow */
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#define QE_MR_IMR_RNTPCOM 0x08 /* runt pkt cnt ovrflw */
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#define QE_MR_IMR_MPCOM 0x04 /* miss pkt cnt ovrflw */
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#define QE_MR_IMR_RCVINTM 0x02 /* rx interrupts */
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#define QE_MR_IMR_XMTINTM 0x01 /* tx interrupts */
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/* qe_mregs.pr: poll register. */
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#define QE_MR_PR_XMTSV 0x80 /* tx status is valid */
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#define QE_MR_PR_TDTREQ 0x40 /* tx data xfer request */
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#define QE_MR_PR_RDTREQ 0x20 /* rx data xfer request */
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/* qe_mregs.biucc: biu config control. */
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#define QE_MR_BIUCC_BSWAP 0x40 /* byte swap */
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#define QE_MR_BIUCC_4TS 0x00 /* 4byte xmit start point */
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#define QE_MR_BIUCC_16TS 0x10 /* 16byte xmit start point */
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#define QE_MR_BIUCC_64TS 0x20 /* 64byte xmit start point */
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#define QE_MR_BIUCC_112TS 0x30 /* 112byte xmit start point */
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#define QE_MR_BIUCC_SWRST 0x01 /* sw-reset mace */
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/* qe_mregs.fifocc: fifo config control. */
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#define QE_MR_FIFOCC_TXF8 0x00 /* tx fifo 8 write cycles */
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#define QE_MR_FIFOCC_TXF32 0x80 /* tx fifo 32 write cycles */
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#define QE_MR_FIFOCC_TXF16 0x40 /* tx fifo 16 write cycles */
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#define QE_MR_FIFOCC_RXF64 0x20 /* rx fifo 64 write cycles */
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#define QE_MR_FIFOCC_RXF32 0x10 /* rx fifo 32 write cycles */
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#define QE_MR_FIFOCC_RXF16 0x00 /* rx fifo 16 write cycles */
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#define QE_MR_FIFOCC_TFWU 0x08 /* tx fifo watermark update */
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#define QE_MR_FIFOCC_RFWU 0x04 /* rx fifo watermark update */
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#define QE_MR_FIFOCC_XMTBRST 0x02 /* tx burst enable */
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#define QE_MR_FIFOCC_RCVBRST 0x01 /* rx burst enable */
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/* qe_mregs.maccc: mac config control. */
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#define QE_MR_MACCC_PROM 0x80 /* promiscuous mode enable */
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#define QE_MR_MACCC_DXMT2PD 0x40 /* tx 2part deferral enable */
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#define QE_MR_MACCC_EMBA 0x20 /* modified backoff enable */
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#define QE_MR_MACCC_DRCVPA 0x08 /* rx physical addr disable */
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#define QE_MR_MACCC_DRCVBC 0x04 /* rx broadcast disable */
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#define QE_MR_MACCC_ENXMT 0x02 /* enable transmitter */
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#define QE_MR_MACCC_ENRCV 0x01 /* enable receiver */
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/* qe_mregs.plscc: pls config control. */
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#define QE_MR_PLSCC_XMTSEL 0x08 /* tx mode select */
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#define QE_MR_PLSCC_PORTMASK 0x06 /* port selection bits */
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#define QE_MR_PLSCC_GPSI 0x06 /* use gpsi connector */
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#define QE_MR_PLSCC_DAI 0x04 /* use dai connector */
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#define QE_MR_PLSCC_TP 0x02 /* use twistedpair connector */
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#define QE_MR_PLSCC_AUI 0x00 /* use aui connector */
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#define QE_MR_PLSCC_ENPLSIO 0x01 /* pls i/o enable */
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/* qe_mregs.phycc: phy config control. */
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#define QE_MR_PHYCC_LNKFL 0x80 /* link fail */
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#define QE_MR_PHYCC_DLNKTST 0x40 /* disable link test logic */
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#define QE_MR_PHYCC_REVPOL 0x20 /* rx polarity */
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#define QE_MR_PHYCC_DAPC 0x10 /* autopolaritycorrect disab */
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#define QE_MR_PHYCC_LRT 0x08 /* select low threshold */
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#define QE_MR_PHYCC_ASEL 0x04 /* connector port auto-sel */
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#define QE_MR_PHYCC_RWAKE 0x02 /* remote wakeup */
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#define QE_MR_PHYCC_AWAKE 0x01 /* auto wakeup */
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/* qe_mregs.iac: internal address config. */
|
||
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#define QE_MR_IAC_ADDRCHG 0x80 /* start address change */
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#define QE_MR_IAC_PHYADDR 0x04 /* physical address reset */
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#define QE_MR_IAC_LOGADDR 0x02 /* logical address reset */
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/* qe_mregs.utr: user test register. */
|
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#define QE_MR_UTR_RTRE 0x80 /* enable resv test register */
|
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#define QE_MR_UTR_RTRD 0x40 /* disab resv test register */
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#define QE_MR_UTR_RPA 0x20 /* accept runt packets */
|
||
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#define QE_MR_UTR_FCOLL 0x10 /* force collision status */
|
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#define QE_MR_UTR_RCVSFCSE 0x08 /* enable fcs on rx */
|
||
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#define QE_MR_UTR_INTLOOPM 0x06 /* Internal loopback w/mandec */
|
||
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#define QE_MR_UTR_INTLOOP 0x04 /* Internal loopback */
|
||
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#define QE_MR_UTR_EXTLOOP 0x02 /* external loopback */
|
||
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#define QE_MR_UTR_NOLOOP 0x00 /* no loopback */
|
||
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|
||
|
|
/* Buffer and Ring sizes: fixed ring size */
|
||
|
|
#define QE_TX_RING_MAXSIZE 256 /* maximum tx ring size */
|
||
|
|
#define QE_RX_RING_MAXSIZE 256 /* maximum rx ring size */
|
||
|
|
#define QE_TX_RING_SIZE 16
|
||
|
|
#define QE_RX_RING_SIZE 16
|
||
|
|
#define QE_PKT_BUF_SZ 2048
|
||
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|
||
|
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#define MC_POLY_LE 0xedb88320 /* mcast crc, little endian */
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