241 lines
7.2 KiB
C
241 lines
7.2 KiB
C
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/* $NetBSD: grf_etreg.h,v 1.1 1996/10/04 07:27:53 leo Exp $ */
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/*
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* Copyright (c) 1996 Tobias Abt
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* Copyright (c) 1995 Ezra Story
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* Copyright (c) 1995 Kari Mettinen
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* Copyright (c) 1994 Markus Wild
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* Copyright (c) 1994 Lutz Vieweg
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Lutz Vieweg.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GRF_ETREG_H
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#define _GRF_ETREG_H
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/*
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* Written & Copyright by Kari Mettinen, Ezra Story.
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*
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* This is derived from Cirrus driver source
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*/
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/*
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* read/write VGA registers
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*/
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#define vgar(ba, reg) (*(((volatile u_char *)ba)+reg))
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#define vgaw(ba, reg, val) *(((volatile u_char *)ba)+reg) = ((u_char)val)
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/*
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* defines for the used register addresses (mw)
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*
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* NOTE: there are some registers that have different addresses when
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* in mono or color mode. We only support color mode, and thus
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* some addresses won't work in mono-mode!
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*
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* General and VGA-registers taken from retina driver. Fixed a few
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* bugs in it. (SR and GR read address is Port + 1, NOT Port)
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*
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*/
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/* General Registers: */
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#define GREG_STATUS0_R 0x03C2
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#define GREG_STATUS1_R 0x03DA
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#define GREG_MISC_OUTPUT_R 0x03CC
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#define GREG_MISC_OUTPUT_W 0x03C2
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#define GREG_FEATURE_CONTROL_R 0x03CA
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#define GREG_FEATURE_CONTROL_W 0x03DA
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#define GREG_POS 0x0102
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#define GREG_HERCULESCOMPAT 0x03BF
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#define GREG_VIDEOSYSENABLE 0x03C3
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#define GREG_DISPMODECONTROL 0x03D8
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#define GREG_COLORSELECT 0x03D9
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#define GREG_ATNTMODECONTROL 0x03DE
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#define GREG_SEGMENTSELECT 0x03CD
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/* Attribute Controller: */
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#define ACT_ADDRESS 0x03C0
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#define ACT_ADDRESS_R 0x03C1
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#define ACT_ADDRESS_W 0x03C0
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#define ACT_ADDRESS_RESET 0x03DA
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#define ACT_ID_PALETTE0 0x00
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#define ACT_ID_PALETTE1 0x01
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#define ACT_ID_PALETTE2 0x02
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#define ACT_ID_PALETTE3 0x03
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#define ACT_ID_PALETTE4 0x04
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#define ACT_ID_PALETTE5 0x05
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#define ACT_ID_PALETTE6 0x06
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#define ACT_ID_PALETTE7 0x07
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#define ACT_ID_PALETTE8 0x08
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#define ACT_ID_PALETTE9 0x09
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#define ACT_ID_PALETTE10 0x0A
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#define ACT_ID_PALETTE11 0x0B
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#define ACT_ID_PALETTE12 0x0C
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#define ACT_ID_PALETTE13 0x0D
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#define ACT_ID_PALETTE14 0x0E
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#define ACT_ID_PALETTE15 0x0F
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#define ACT_ID_ATTR_MODE_CNTL 0x10
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#define ACT_ID_OVERSCAN_COLOR 0x11
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#define ACT_ID_COLOR_PLANE_ENA 0x12
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#define ACT_ID_HOR_PEL_PANNING 0x13
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#define ACT_ID_COLOR_SELECT 0x14
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#define ACT_ID_MISCELLANEOUS 0x16
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/* Graphics Controller: */
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#define GCT_ADDRESS 0x03CE
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#define GCT_ADDRESS_R 0x03CF
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#define GCT_ADDRESS_W 0x03CF
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#define GCT_ID_SET_RESET 0x00
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#define GCT_ID_ENABLE_SET_RESET 0x01
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#define GCT_ID_COLOR_COMPARE 0x02
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#define GCT_ID_DATA_ROTATE 0x03
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#define GCT_ID_READ_MAP_SELECT 0x04
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#define GCT_ID_GRAPHICS_MODE 0x05
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#define GCT_ID_MISC 0x06
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#define GCT_ID_COLOR_XCARE 0x07
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#define GCT_ID_BITMASK 0x08
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/* Sequencer: */
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#define SEQ_ADDRESS 0x03C4
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#define SEQ_ADDRESS_R 0x03C5
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#define SEQ_ADDRESS_W 0x03C5
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#define SEQ_ID_RESET 0x00
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#define SEQ_ID_CLOCKING_MODE 0x01
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#define SEQ_ID_MAP_MASK 0x02
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#define SEQ_ID_CHAR_MAP_SELECT 0x03
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#define SEQ_ID_MEMORY_MODE 0x04
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#define SEQ_ID_STATE_CONTROL 0x06
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#define SEQ_ID_AUXILIARY_MODE 0x07
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/* CRT Controller: */
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#define CRT_ADDRESS 0x03D4
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#define CRT_ADDRESS_R 0x03D5
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#define CRT_ADDRESS_W 0x03D5
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#define CRT_ID_HOR_TOTAL 0x00
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#define CRT_ID_HOR_DISP_ENA_END 0x01
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#define CRT_ID_START_HOR_BLANK 0x02
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#define CRT_ID_END_HOR_BLANK 0x03
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#define CRT_ID_START_HOR_RETR 0x04
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#define CRT_ID_END_HOR_RETR 0x05
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#define CRT_ID_VER_TOTAL 0x06
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#define CRT_ID_OVERFLOW 0x07
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#define CRT_ID_PRESET_ROW_SCAN 0x08
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#define CRT_ID_MAX_ROW_ADDRESS 0x09
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#define CRT_ID_CURSOR_START 0x0A
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#define CRT_ID_CURSOR_END 0x0B
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#define CRT_ID_START_ADDR_HIGH 0x0C
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#define CRT_ID_START_ADDR_LOW 0x0D
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#define CRT_ID_CURSOR_LOC_HIGH 0x0E
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#define CRT_ID_CURSOR_LOC_LOW 0x0F
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#define CRT_ID_START_VER_RETR 0x10
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#define CRT_ID_END_VER_RETR 0x11
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#define CRT_ID_VER_DISP_ENA_END 0x12
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#define CRT_ID_OFFSET 0x13
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#define CRT_ID_UNDERLINE_LOC 0x14
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#define CRT_ID_START_VER_BLANK 0x15
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#define CRT_ID_END_VER_BLANK 0x16
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#define CRT_ID_MODE_CONTROL 0x17
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#define CRT_ID_LINE_COMPARE 0x18
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#define CRT_ID_SEGMENT_COMP 0x30
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#define CRT_ID_GENERAL_PURPOSE 0x31
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#define CRT_ID_RASCAS_CONFIG 0x32
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#define CTR_ID_EXT_START 0x33
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#define CRT_ID_6845_COMPAT 0x34
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#define CRT_ID_OVERFLOW_HIGH 0x35
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#define CRT_ID_VIDEO_CONFIG1 0x36
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#define CRT_ID_VIDEO_CONFIG2 0x37
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#define CRT_ID_HOR_OVERFLOW 0x3f
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/* Video DAC */
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#define VDAC_ADDRESS 0x03c8
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#define VDAC_ADDRESS_W 0x03c8
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#define VDAC_ADDRESS_R 0x03c7
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#define VDAC_STATE 0x03c7
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#define VDAC_DATA 0x03c9
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#define VDAC_MASK 0x03c6
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#define HDR 0x03c6 /* Hidden DAC regs, 4 reads to access */
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#define VDAC_COMMAND 0x03c6
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#define VDAC_XINDEX 0x03c7
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#define VDAC_XDATA 0x03c8
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#define WGfx(ba, idx, val) \
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do { \
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vgaw(ba, GCT_ADDRESS, idx); \
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vgaw(ba, GCT_ADDRESS_W , val); \
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} while (0)
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#define WSeq(ba, idx, val) \
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do { \
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vgaw(ba, SEQ_ADDRESS, idx); \
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vgaw(ba, SEQ_ADDRESS_W , val); \
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} while (0)
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#define WCrt(ba, idx, val) \
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do { \
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vgaw(ba, CRT_ADDRESS, idx); \
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vgaw(ba, CRT_ADDRESS_W , val); \
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} while (0)
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#define WIma(ba, idx, val) \
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do { \
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vgaw(ba, IMA_ADDRESS, idx); \
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vgaw(ba, IMA_ADDRESS_W , val); \
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} while (0)
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#define WAttr(ba, idx, val) \
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do { \
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if(vgar(ba, GREG_STATUS1_R)) \
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; \
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vgaw(ba, ACT_ADDRESS_W, idx); \
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vgaw(ba, ACT_ADDRESS_W, val); \
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} while (0)
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static inline u_char RAttr(volatile void * ba, short idx) {
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if(vgar(ba, GREG_STATUS1_R))
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;
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vgaw(ba, ACT_ADDRESS_W, idx);
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return vgar(ba, ACT_ADDRESS_R);
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}
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static inline u_char RSeq(volatile void * ba, short idx) {
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vgaw(ba, SEQ_ADDRESS, idx);
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return vgar(ba, SEQ_ADDRESS_R);
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}
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static inline u_char RCrt(volatile void * ba, short idx) {
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vgaw(ba, CRT_ADDRESS, idx);
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return vgar(ba, CRT_ADDRESS_R);
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}
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static inline u_char RGfx(volatile void * ba, short idx) {
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vgaw(ba, GCT_ADDRESS, idx);
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return vgar(ba, GCT_ADDRESS_R);
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}
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#endif /* _GRF_ETREG_H */
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