2003-03-12 16:36:22 +03:00
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/* $NetBSD: ydsreg.h,v 1.4 2003/03/12 13:36:23 minoura Exp $ */
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2001-03-30 18:32:08 +04:00
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/*
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* Copyright (c) 2000, 2001 Kazuki Sakamoto and Minoura Makoto.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* YMF724/740/744/754 registers
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*/
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#ifndef _DEV_PCI_YDSREG_H_
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#define _DEV_PCI_YDSREG_H_
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/*
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* PCI Config Registers
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*/
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#define YDS_PCI_MBA 0x10
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#define YDS_PCI_LEGACY 0x40
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# define YDS_PCI_LEGACY_SBEN 0x0001
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# define YDS_PCI_LEGACY_FMEN 0x0002
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# define YDS_PCI_LEGACY_JPEN 0x0004
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# define YDS_PCI_LEGACY_MEN 0x0008
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# define YDS_PCI_LEGACY_MIEN 0x0010
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# define YDS_PCI_LEGACY_IO 0x0020
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# define YDS_PCI_LEGACY_SDMA0 0x0000
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# define YDS_PCI_LEGACY_SDMA1 0x0040
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# define YDS_PCI_LEGACY_SDMA3 0x00c0
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# define YDS_PCI_LEGACY_SBIRQ5 0x0000
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# define YDS_PCI_LEGACY_SBIRQ7 0x0100
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# define YDS_PCI_LEGACY_SBIRQ9 0x0200
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# define YDS_PCI_LEGACY_SBIRQ10 0x0300
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# define YDS_PCI_LEGACY_SBIRQ11 0x0400
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# define YDS_PCI_LEGACY_MPUIRQ5 0x0000
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# define YDS_PCI_LEGACY_MPUIRQ7 0x0800
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# define YDS_PCI_LEGACY_MPUIRQ9 0x1000
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# define YDS_PCI_LEGACY_MPUIRQ10 0x1800
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# define YDS_PCI_LEGACY_MPUIRQ11 0x2000
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# define YDS_PCI_LEGACY_SIEN 0x4000
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# define YDS_PCI_LEGACY_LAD 0x8000
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# define YDS_PCI_EX_LEGACY_FMIO_388 (0x0000 << 16)
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# define YDS_PCI_EX_LEGACY_FMIO_398 (0x0001 << 16)
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# define YDS_PCI_EX_LEGACY_FMIO_3A0 (0x0002 << 16)
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# define YDS_PCI_EX_LEGACY_FMIO_3A8 (0x0003 << 16)
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# define YDS_PCI_EX_LEGACY_SBIO_220 (0x0000 << 16)
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# define YDS_PCI_EX_LEGACY_SBIO_240 (0x0004 << 16)
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# define YDS_PCI_EX_LEGACY_SBIO_260 (0x0008 << 16)
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# define YDS_PCI_EX_LEGACY_SBIO_280 (0x000c << 16)
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# define YDS_PCI_EX_LEGACY_MPUIO_330 (0x0000 << 16)
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# define YDS_PCI_EX_LEGACY_MPUIO_300 (0x0010 << 16)
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# define YDS_PCI_EX_LEGACY_MPUIO_332 (0x0020 << 16)
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# define YDS_PCI_EX_LEGACY_MPUIO_334 (0x0030 << 16)
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# define YDS_PCI_EX_LEGACY_JSIO_201 (0x0000 << 16)
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# define YDS_PCI_EX_LEGACY_JSIO_202 (0x0040 << 16)
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# define YDS_PCI_EX_LEGACY_JSIO_204 (0x0080 << 16)
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# define YDS_PCI_EX_LEGACY_JSIO_205 (0x00c0 << 16)
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# define YDS_PCI_EX_LEGACY_MAIM (0x0100 << 16)
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2003-03-12 16:28:19 +03:00
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# define YDS_PCI_EX_LEGACY_SMOD_PCI (0x0000 << 16)
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2003-03-12 16:36:22 +03:00
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# define YDS_PCI_EX_LEGACY_SMOD_DISABLE (0x0800 << 16)
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2003-03-12 16:28:19 +03:00
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# define YDS_PCI_EX_LEGACY_SMOD_DDMA (0x1000 << 16)
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2001-03-30 18:32:08 +04:00
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# define YDS_PCI_EX_LEGACY_SBVER_3 (0x0000 << 16)
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# define YDS_PCI_EX_LEGACY_SBVER_2 (0x2000 << 16)
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# define YDS_PCI_EX_LEGACY_SBVER_1 (0x4000 << 16)
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# define YDS_PCI_EX_LEGACY_IMOD (0x8000 << 16)
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#define YDS_PCI_DSCTRL 0x48
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2002-11-04 17:56:10 +03:00
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# define YDS_DSCTRL_CRST 0x0001
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# define YDS_DSCTRL_WRST 0x0004
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# define YDS_DSCTRL_ACLS 0x0008
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#define YDS_PCI_DSPOWER1 0x4a
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# define YDS_DSPOWER1_DMC 0x0001
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# define YDS_DSPOWER1_DPLL 0x0002
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# define YDS_DSPOWER1_JSR 0x0040
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#define YDS_PCI_DISTDMA 0x4c
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#define YDS_PCI_DSPOWER2 0x4e
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# define YDS_DSPOWER2_CMCD 0x0001
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# define YDS_DSPOWER2_PSFM 0x0002
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# define YDS_DSPOWER2_PSSB 0x0004
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# define YDS_DSPOWER2_PSMPU 0x0008
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# define YDS_DSPOWER2_PSJOY 0x0010
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# define YDS_DSPOWER2_PSPCA 0x0020
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# define YDS_DSPOWER2_PSSRC 0x0040
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# define YDS_DSPOWER2_PSZV 0x0080
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# define YDS_DSPOWER2_PSDIT 0x0100
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# define YDS_DSPOWER2_PSDIR 0x0200
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# define YDS_DSPOWER2_PSACL 0x0400
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# define YDS_DSPOWER2_PSIO 0x0800
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# define YDS_DSPOWER2_PSHWV 0x1000
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2001-03-30 18:32:08 +04:00
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#define YDS_PCI_FM_BA 0x60
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#define YDS_PCI_SB_BA 0x62
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#define YDS_PCI_MPU_BA 0x64
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#define YDS_PCI_JS_BA 0x66
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/*
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* DS-1 PCI Audio part registers
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*/
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#define YDS_INTERRUPT_FLAGS 0x0004
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#define YDS_INTERRUPT_FLAGS_TI 0x0001
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#define YDS_ACTIVITY 0x0006
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# define YDS_ACTIVITY_DOCKA 0x0010
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#define YDS_GLOBAL_CONTROL 0x0008
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# define YDS_GLCTRL_HVE 0x0001
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# define YDS_GLCTRL_HVIE 0x0002
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#define YDS_GPIO_IIF 0x0050
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# define YDS_GPIO_GIO0 0x0001
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# define YDS_GPIO_GIO1 0x0002
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# define YDS_GPIO_GIO2 0x0004
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#define YDS_GPIO_IIE 0x0052
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# define YDS_GPIO_GIE0 0x0001
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# define YDS_GPIO_GIE1 0x0002
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# define YDS_GPIO_GIE2 0x0004
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#define YDS_GPIO_ISTAT 0x0054
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# define YDS_GPIO_GPI0 0x0001
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# define YDS_GPIO_GPI1 0x0002
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# define YDS_GPIO_GPI2 0x0004
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#define YDS_GPIO_OCTRL 0x0056
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# define YDS_GPIO_GPO0 0x0001
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# define YDS_GPIO_GPO1 0x0002
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# define YDS_GPIO_GPO2 0x0004
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#define YDS_GPIO_FUNCE 0x0058
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# define YDS_GPIO_GPC0 0x0001
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# define YDS_GPIO_GPC1 0x0002
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# define YDS_GPIO_GPC2 0x0004
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# define YDS_GPIO_GPE0 0x0010
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# define YDS_GPIO_GPE1 0x0020
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# define YDS_GPIO_GPE2 0x0040
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#define YDS_GPIO_ITYPE 0x005a
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# define YDS_GPIO_GPT0_LEVEL 0x0000
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# define YDS_GPIO_GPT0_RISE 0x0001
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# define YDS_GPIO_GPT0_FALL 0x0002
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# define YDS_GPIO_GPT0_BOTH 0x0003
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# define YDS_GPIO_GPT0_MASK 0x0003
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# define YDS_GPIO_GPT1_LEVEL 0x0004
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# define YDS_GPIO_GPT1_RISE 0x0005
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# define YDS_GPIO_GPT1_FALL 0x0006
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# define YDS_GPIO_GPT1_BOTH 0x0007
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# define YDS_GPIO_GPT1_MASK 0x0007
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# define YDS_GPIO_GPT2_LEVEL 0x0000
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# define YDS_GPIO_GPT2_RISE 0x0010
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# define YDS_GPIO_GPT2_FALL 0x0020
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# define YDS_GPIO_GPT2_BOTH 0x0030
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# define YDS_GPIO_GPT2_MASK 0x0030
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#define YDS_GLOBAL_CONTROL 0x0008
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# define YDS_GLCTRL_HVE 0x0001
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# define YDS_GLCTRL_HVIE 0x0002
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#define AC97_CMD_DATA 0x0060
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#define AC97_CMD_ADDR 0x0062
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# define AC97_ID(id) ((id) << 8)
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# define AC97_CMD_READ 0x8000
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# define AC97_CMD_WRITE 0x0000
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#define AC97_STAT_DATA1 0x0064
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#define AC97_STAT_ADDR1 0x0066
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#define AC97_STAT_DATA2 0x0068
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#define AC97_STAT_ADDR2 0x006a
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# define AC97_BUSY 0x8000
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2002-11-04 17:56:10 +03:00
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#define AC97_SECONDARY_CONF 0x0070
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# define AC97_SECONDARY_RSOC 0x0001
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# define AC97_SECONDARY_PHWV 0x0002
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# define AC97_SECONDARY_SHWV 0x0004
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# define AC97_SECONDARY_4CHEN 0x0010
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# define AC97_SECONDARY_4CHSEL 0x0020
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2001-03-30 18:32:08 +04:00
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#define YDS_LEGACY_OUT_VOLUME 0x0080
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#define YDS_DAC_OUT_VOLUME 0x0084
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#define YDS_DAC_OUT_VOL_L 0x0084
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#define YDS_DAC_OUT_VOL_R 0x0086
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#define YDS_ZV_OUT_VOLUME 0x0088
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#define YDS_2ND_OUT_VOLUME 0x008C
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#define YDS_ADC_OUT_VOLUME 0x0090
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#define YDS_LEGACY_REC_VOLUME 0x0094
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#define YDS_DAC_REC_VOLUME 0x0098
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#define YDS_ZV_REC_VOLUME 0x009C
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#define YDS_2ND_REC_VOLUME 0x00A0
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#define YDS_ADC_REC_VOLUME 0x00A4
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#define YDS_ADC_IN_VOLUME 0x00A8
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#define YDS_REC_IN_VOLUME 0x00AC
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#define YDS_P44_OUT_VOLUME 0x00B0
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#define YDS_P44_REC_VOLUME 0x00B4
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#define YDS_SPDIFIN_OUT_VOLUME 0x00B8
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#define YDS_SPDIFIN_REC_VOLUME 0x00BC
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#define YDS_ADC_SAMPLE_RATE 0x00c0
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#define YDS_REC_SAMPLE_RATE 0x00c4
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#define YDS_ADC_FORMAT 0x00c8
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#define YDS_REC_FORMAT 0x00cc
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# define YDS_FORMAT_8BIT 0x01
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# define YDS_FORMAT_STEREO 0x02
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#define YDS_STATUS 0x0100
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# define YDS_STAT_ACT 0x00000001
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# define YDS_STAT_WORK 0x00000002
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# define YDS_STAT_TINT 0x00008000
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# define YDS_STAT_INT 0x80000000
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#define YDS_CONTROL_SELECT 0x0104
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# define YDS_CSEL 0x00000001
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#define YDS_MODE 0x0108
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# define YDS_MODE_ACTV 0x00000001
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# define YDS_MODE_ACTV2 0x00000002
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# define YDS_MODE_TOUT 0x00008000
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# define YDS_MODE_RESET 0x00010000
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# define YDS_MODE_AC3 0x40000000
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# define YDS_MODE_MUTE 0x80000000
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#define YDS_CONFIG 0x0114
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# define YDS_DSP_DISABLE 0
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# define YDS_DSP_SETUP 0x00000001
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#define YDS_PLAY_CTRLSIZE 0x0140
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#define YDS_REC_CTRLSIZE 0x0144
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#define YDS_EFFECT_CTRLSIZE 0x0148
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#define YDS_WORK_SIZE 0x014c
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#define YDS_MAPOF_REC 0x0150
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# define YDS_RECSLOT_VALID 0x00000001
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# define YDS_ADCSLOT_VALID 0x00000002
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#define YDS_MAPOF_EFFECT 0x0154
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# define YDS_DL_VALID 0x00000001
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# define YDS_DR_VALID 0x00000002
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# define YDS_EFFECT1_VALID 0x00000004
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# define YDS_EFFECT2_VALID 0x00000008
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# define YDS_EFFECT3_VALID 0x00000010
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#define YDS_PLAY_CTRLBASE 0x0158
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#define YDS_REC_CTRLBASE 0x015c
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#define YDS_EFFECT_CTRLBASE 0x0160
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#define YDS_WORK_BASE 0x0164
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#define YDS_DSP_INSTRAM 0x1000
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#define YDS_CTRL_INSTRAM 0x4000
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typedef enum {
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YDS_DS_1,
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YDS_DS_1E
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} yds_dstype_t;
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#define AC97_TIMEOUT 1000
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#define YDS_WORK_TIMEOUT 250000
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/* slot control data structures */
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#define MAX_PLAY_SLOT_CTRL 64
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#define N_PLAY_SLOT_CTRL_BANK 2
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#define N_REC_SLOT_CTRL 2
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#define N_REC_SLOT_CTRL_BANK 2
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/*
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* play slot
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*/
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union play_slot_table {
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u_int32_t numofplay;
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u_int32_t slotbase;
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};
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struct play_slot_ctrl_bank {
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u_int32_t format;
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#define PSLT_FORMAT_STEREO 0x00010000
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#define PSLT_FORMAT_8BIT 0x80000000
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#define PSLT_FORMAT_SRC441 0x10000000
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#define PSLT_FORMAT_RCH 0x00000001
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u_int32_t loopdefault;
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u_int32_t pgbase;
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u_int32_t pgloop;
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u_int32_t pgloopend;
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u_int32_t pgloopfrac;
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u_int32_t pgdeltaend;
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u_int32_t lpfkend;
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u_int32_t eggainend;
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u_int32_t lchgainend;
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u_int32_t rchgainend;
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u_int32_t effect1gainend;
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u_int32_t effect2gainend;
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u_int32_t effect3gainend;
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u_int32_t lpfq;
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u_int32_t status;
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#define PSLT_STATUS_DEND 0x00000001
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u_int32_t numofframes;
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u_int32_t loopcount;
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u_int32_t pgstart;
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u_int32_t pgstartfrac;
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u_int32_t pgdelta;
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u_int32_t lpfk;
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u_int32_t eggain;
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u_int32_t lchgain;
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u_int32_t rchgain;
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u_int32_t effect1gain;
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u_int32_t effect2gain;
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u_int32_t effect3gain;
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u_int32_t lpfd1;
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u_int32_t lpfd2;
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};
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/*
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* rec slot
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*/
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struct rec_slot_ctrl_bank {
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u_int32_t pgbase;
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u_int32_t pgloopendadr;
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u_int32_t pgstartadr;
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u_int32_t numofloops;
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};
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struct rec_slot {
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struct rec_slot_ctrl {
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struct rec_slot_ctrl_bank bank[N_REC_SLOT_CTRL_BANK];
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} ctrl[N_REC_SLOT_CTRL];
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};
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/*
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* effect slot
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*/
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struct effect_slot_ctrl_bank {
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u_int32_t pgbase;
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u_int32_t pgloopend;
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u_int32_t pgstart;
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u_int32_t temp;
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};
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#endif /* _DEV_PCI_YDSREG_H_ */
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