119 lines
4.2 KiB
C
119 lines
4.2 KiB
C
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/* $Id: at91pmcreg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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#ifndef _AT91PMCREG_H_
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#define _AT91PMCREG_H_ 1
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/* Power Management Controller (PMC), at,
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* at91rm9200.pdf, page 271 */
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#define PMC_NUM_PCLOCKS 8
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#define PMC_SCER 0x00U /* 00: System Clock Enable Reg */
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#define PMC_SCDR 0x04U /* 04: System Clock Disable Reg */
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#define PMC_SCSR 0x08U /* 08: System Clock Status Reg */
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#define PMC_PCER 0x10U /* 10: Peripheral Clock Enable */
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#define PMC_PCDR 0x14U /* 14: Peripheral Clock Disable */
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#define PMC_PCSR 0x18U /* 18: Peripheral Clock Status */
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#define PMC_MOR 0x20U /* 20: Main Oscillator Reg */
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#define PMC_MCFR 0x24U /* 24: Main Clock Freq Reg */
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#define PMC_PLLAR 0x28U /* 28: PLL A Register#define PMC_*/
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#define PMC_PLLBR 0x2CU /* 2C: PLL B Register */
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#define PMC_MCKR 0x30U /* 30: Master Clock Register */
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#define PMC_PCK(num) (0x40U + (num) * 4U) /* 40: Programmable Clocks */
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#define PMC_IER 0x60U /* 60: Interrupt Enable Reg */
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#define PMC_IDR 0x64U /* 64: Interrupt Disable Reg */
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#define PMC_SR 0x68U /* 68: Status Register */
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#define PMC_IMR 0x6CU /* 6C: Interrupt Mask Reg */
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/* System Clock Enable Register bits: */
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#define PMC_SCSR_PCK3 0x0800U
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#define PMC_SCSR_PCK2 0x0400U
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#define PMC_SCSR_PCK1 0x0200U
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#define PMC_SCSR_PCK0 0x0100U
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#define PMC_SCSR_UHP 0x0010U /* 1 = Enable USB Host Port clks */
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#define PMC_SCSR_MCKUDP 0x0004U /* 1 = enable Master Clock dis */
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#define PMC_SCSR_UDP 0x0002U /* 1 = enable USB Device Port clk */
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#define PMC_SCSR_PCK 0x0001U /* 1 = enable the processor clk */
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/* Main Oscillator Register bits: */
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#define PMC_MOR_OSCOUNT 0xFF00U /* start-up-time / 8 */
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#define PMC_MOR_OSCOUNT_SHIFT 8U
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#define PMC_MOR_MOSCEN 0x1U /* 1 = main oscillator enabled */
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/* Main Clock Frequency Register bits: */
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#define PMC_MCFR_MAINRDY 0x10000U /* 1= main clock ready */
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#define PMC_MCFR_MAINF 0x0FFFFU
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/* PLL Register bits: */
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#define PMC_PLL_MUL 0x07FF0000U
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#define PMC_PLL_MUL_SHIFT 16U
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#define PMC_PLL_OUT 0x0000C000U
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#define PMC_PLL_OUT_80_TO_160 0x00000000U
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#define PMC_PLL_OUT_150_TO_240 0x00008000U
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#define PMC_PLL_PLLCOUNT 0x00003F00U
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#define PMC_PLL_DIV 0x000000FFU
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#define PMC_PLL_DIV_SHIFT 0U
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/* PLL B Register bits: */
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#define PMC_PLLBR_USB_96M 0x10000000U /* 1 = USB clks = PLL B output / 2 */
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/* Master Clock Register bits: */
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#define PMC_MCKR_MDIV 0x300U
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#define PMC_MCKR_MDIV_1 0x000U
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#define PMC_MCKR_MDIV_2 0x100U
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#define PMC_MCKR_MDIV_3 0x200U
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#define PMC_MCKR_MDIV_4 0x300U
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#define PMC_MCKR_MDIV_SHIFT 8U
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#define PMC_MCKR_PRES 0x01CU
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#define PMC_MCKR_PRES_SHIFT 2U
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#define PMC_MCKR_PRES_1 (0U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_2 (1U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_4 (2U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_8 (3U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_16 (4U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_32 (5U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_PRES_64 (6U<<PMC_MCKR_PRES_SHIFT)
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#define PMC_MCKR_CSS 0x003U
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#define PMC_MCKR_CSS_SLOW_CLK 0x000U
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#define PMC_MCKR_CSS_MAIN_CLK 0x001U
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#define PMC_MCKR_CSS_PLLA 0x002U
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#define PMC_MCKR_CSS_PLLB 0x003U
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/* Programmable Clock Register bits: */
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#define PMC_PCK_PRES PMC_MCKR_PRES
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#define PMC_PCK_PRES_SHIFT PMC_MCKR_PRES_SHIFT
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#define PMC_PCK_PRES_1 PMC_MCKR_PRES_1
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#define PMC_PCK_PRES_2 PMC_MCKR_PRES_2
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#define PMC_PCK_PRES_4 PMC_MCKR_PRES_4
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#define PMC_PCK_PRES_8 PMC_MCKR_PRES_8
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#define PMC_PCK_PRES_16 PMC_MCKR_PRES_16
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#define PMC_PCK_PRES_32 PMC_MCKR_PRES_32
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#define PMC_PCK_PRES_64 PMC_MCKR_PRES_64
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#define PMC_PCK_CSS PMC_MCKR_CSS
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#define PMC_PCK_CSS_SLOW_CLK PMC_MCKR_CSS_SLOW_CLK
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#define PMC_PCK_CSS_CLKC PMC_MCKR_CSS_CLKC
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#define PMC_PCK_CSS_CLKA PMC_MCKR_CSS_CLKA
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#define PMC_PCK_CSS_CLKB PMC_MCKR_CSS_CLKB
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/* Interrupt Enable Register bits: */
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#define PMC_SR_PCK7RDY 0x8000U
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#define PMC_SR_PCK6RDY 0x4000U
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#define PMC_SR_PCK5RDY 0x2000U
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#define PMC_SR_PCK4RDY 0x1000U
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#define PMC_SR_PCK3RDY 0x0800U
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#define PMC_SR_PCK2RDY 0x0400U
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#define PMC_SR_PCK1RDY 0x0200U
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#define PMC_SR_PCK0RDY 0x0100U
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#define PMC_SR_MCKRDY 0x0008U
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#define PMC_SR_LOCKB 0x0004U
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#define PMC_SR_LOCKA 0x0002U
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#define PMC_SR_MOSCS 0x0001U
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#define PMCREG(offset) *((volatile uint32_t*)(0xfffffc00UL + (offset)))
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#endif /* !_AT91PMCREG_H_ */
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