96 lines
4.6 KiB
C
96 lines
4.6 KiB
C
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/* $NetBSD: timekeeper.h,v 1.1 2000/01/05 08:48:56 nisimura Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tohru Nishimura.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Mostek MK48T02 for LUNA-1
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*/
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#define MK_CSR 0 /* control register */
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#define MK_SEC 1 /* seconds (0..59; BCD) */
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#define MK_MIN 2 /* minutes (0..59; BCD) */
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#define MK_HOUR 3 /* hour (0..23; BCD) */
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#define MK_DOW 4 /* weekday (1..7) */
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#define MK_DOM 5 /* day in month (1..31; BCD) */
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#define MK_MONTH 6 /* month (1..12; BCD) */
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#define MK_YEAR 7 /* year (0..99; BCD) */
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/* bits in cl_csr */
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#define MK_CSR_WRITE 0x80 /* want to write */
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#define MK_CSR_READ 0x40 /* want to read (freeze clock) */
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/*
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* Dallas Semiconductor DS1287 -- mc146818 compatible, for LUNA-2
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*/
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#define MC_SEC 0x0 /* Time of year: seconds (0-59) */
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#define MC_ASEC 0x1 /* Alarm: seconds */
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#define MC_MIN 0x2 /* Time of year: minutes (0-59) */
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#define MC_AMIN 0x3 /* Alarm: minutes */
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#define MC_HOUR 0x4 /* Time of year: hour (see above) */
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#define MC_AHOUR 0x5 /* Alarm: hour */
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#define MC_DOW 0x6 /* Time of year: day of week (1-7) */
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#define MC_DOM 0x7 /* Time of year: day of month (1-31) */
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#define MC_MONTH 0x8 /* Time of year: month (1-12) */
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#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */
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#define MC_REGA 0xa /* Control register A */
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#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */
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#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */
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#define MC_REGA_UIP 0x80 /* Update in progress; read only. */
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#define MC_REGB 0xb /* Control register B */
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#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */
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#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */
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#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */
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#define MC_REGB_SQWE 0x08 /* Square Wave Enable */
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#define MC_REGB_UIE 0x10 /* Update End interrupt enable */
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#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */
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#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */
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#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */
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#define MC_REGC 0xc /* Control register C */
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/* MC_REGC_UNUSED 0x0f UNUSED */
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#define MC_REGC_UF 0x10 /* Update End interrupt flag */
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#define MC_REGC_AF 0x20 /* Alarm interrupt flag */
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#define MC_REGC_PF 0x40 /* Periodic interrupt flag */
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#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */
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#define MC_REGD 0xd /* Control register D */
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/* MC_REGD_UNUSED 0x7f UNUSED */
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#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */
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#define MC_NREGS 0xe /* 14 registers; CMOS follows */
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#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */
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