2005-12-11 15:16:03 +03:00
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/* $NetBSD: cs4231reg.h,v 1.10 2005/12/11 12:21:26 christos Exp $ */
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1996-02-05 03:10:32 +03:00
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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1995-07-07 06:11:45 +04:00
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*
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1996-02-05 03:10:32 +03:00
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ken Hornstein and John Kohl.
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1995-07-07 06:11:45 +04:00
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*
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1996-02-05 03:10:32 +03:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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2005-02-27 03:26:58 +03:00
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* This product includes software developed by the NetBSD
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1996-02-05 03:10:32 +03:00
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* Foundation, Inc. and its contributors.
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2005-02-27 03:26:58 +03:00
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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1996-02-05 03:10:32 +03:00
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* from this software without specific prior written permission.
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1995-07-07 06:11:45 +04:00
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*
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1996-02-05 05:18:48 +03:00
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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1997-10-09 12:03:42 +04:00
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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1996-02-05 05:18:48 +03:00
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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1995-07-07 06:11:45 +04:00
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*/
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/*
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* Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer
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* chip, used on Gravis UltraSound MAX cards.
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*
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* Block diagram:
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* +----------------------------------------------------+
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1999-04-07 14:21:31 +04:00
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* | |
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1995-07-07 06:11:45 +04:00
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* | +----------------------------------------------+ |
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1999-04-07 14:21:31 +04:00
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* | |mixed in +-+ | |
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* | +------------>--| | | |
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* | mic in | | | |
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* Mic --+-->| --------- GAIN ->-| | | |
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* | | AUX 1 in |M| | |
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* GF1 --)-->| -------------+-->-|U| | |
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* | | Line in | |X|---- GAIN ----------+ | |
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* Line --)-->| ---------+---)-->-| | | | |
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* | | | | | | | | |
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* | | | | +-+ ADC | |
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* | | | | | | |
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* | | | | | | |
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* | | | +--- L/M --\ | | | AMP-->
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* | | | \ | | | |
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* | | | \ | | | |
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* | | +---- L/M -------O-->--+--------)-------+-|--+-> line
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* | | mono in /| | | |
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* +---|-->------------ L/M -----/ | | | |
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* | AUX 2 in | | | |
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* CD --------|-->------------ L/M -------+ L/M | |
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* | | v |
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* | | | |
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* | DAC | |
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* | | | |
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* +----------------------------------------------------+
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* | |
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* | |
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* v v
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* Pc BUS (DISK) ???
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*
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*/
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/* CS4231/AD1845 mode2 registers; added to AD1848 registers */
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#define CS_ALT_FEATURE1 16
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#define CS_ALT_FEATURE2 17
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#define CS_LEFT_LINE_CONTROL 18
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#define CS_RIGHT_LINE_CONTROL 19
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#define CS_TIMER_LOW 20
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#define CS_TIMER_HIGH 21
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#define CS_UPPER_FREQUENCY_SEL 22
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#define CS_LOWER_FREQUENCY_SEL 23
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#define CS_IRQ_STATUS 24
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#define CS_VERSION_ID 25
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#define CS_MONO_IO_CONTROL 26
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#define CS_POWERDOWN_CONTROL 27
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#define CS_REC_FORMAT 28
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#define CS_XTAL_SELECT 29
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#define CS_UPPER_REC_CNT 30
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#define CS_LOWER_REC_CNT 31
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1998-08-27 23:53:02 +04:00
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/* ALT_FEATURE1 - register I16 */
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#define ALT_F1_DACZ 0x01 /* 1: hold sample during underrun */
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#define ALT_F1_SPE 0x02 /* 1: Serial port enable */
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#define ALT_F1_SFORMAT 0x06 /* Serial port format */
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#define ALT_F1_PMCE 0x10 /* Playback mode change enable */
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#define ALT_F1_CMCE 0x20 /* Capture mode change enable */
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#define ALT_F1_TE 0x40 /* Timer enable */
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#define ALT_F1_OLB 0x80 /* Output level bit */
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1998-08-27 23:53:02 +04:00
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/* ALT_FEATURE2 - register I17 */
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#define ALT_F2_HPF 0x01 /* High pass filter */
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#define ALT_F2_XTALE 0x02 /* Crytal enable */
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#define ALT_F2_APAR 0x04 /* ADPCM playback accumulator reset */
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#define ALT_F2_RES 0x08 /* reserved */
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#define ALT_F2_TEST 0xf0 /* Factory test bits */
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/* LINE_CONTROL (LEFT & RIGHT) - register I18,I19 */
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#define LINE_INPUT_ATTEN_BITS 0x1f
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#define LINE_INPUT_ATTEN_MASK 0xe0
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#define LINE_INPUT_MUTE 0x80
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#define LINE_INPUT_MUTE_MASK (~LINE_INPUT_MUTE & 0xff)
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/* ALT_FEATURE3 - register I23 */
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#define ALT_F3_ACF 0x01 /* ADPCM capture freeze */
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/* ALT_FEATURE_STATUS (aka CS_IRQ_STATUS) - register I24 */
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#define CS_IRQ_PU 0x01 /* Playback Underrun */
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#define CS_IRQ_PO 0x02 /* Playback Overrun */
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#define CS_IRQ_CO 0x04 /* Capture Overrun */
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#define CS_IRQ_CU 0x08 /* Capture Underrun */
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#define CS_IRQ_PI 0x10 /* Playback Interrupt */
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#define CS_IRQ_CI 0x20 /* Capture Interrupt */
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#define CS_IRQ_TI 0x40 /* Timer Interrupt */
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#define CS_IRQ_RES 0x80 /* reserved */
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1998-08-28 00:05:11 +04:00
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#define CS_I24_BITS "\20\1PU\2PO\3CO\4CU\5PI\6CI\7TI"
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1998-08-27 23:53:02 +04:00
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/* VERSION - register I25 */
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#define CS_VERSION_NUMBER 0xe0 /* Version number:
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* 0x101 - 4231 rev. A
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* 0x100 - 4231 previous revs
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*/
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#define CS_VERSION_CHIPID 0x07 /* Chip Identification.
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* Currently know values: 0x000
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*/
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/* MONO_IO_CONTROL - register I26 */
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#define MONO_INPUT_ATTEN_BITS 0x0f
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#define MONO_INPUT_ATTEN_MASK 0xf0
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#define MONO_BYPASS 0x20
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#define MONO_OUTPUT_MUTE 0x40
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#define MONO_OUTPUT_MUTE_MASK (~MONO_OUTPUT_MUTE & 0xff)
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#define MONO_INPUT_MUTE 0x80
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#define MONO_INPUT_MUTE_MASK (~MONO_INPUT_MUTE & 0xff)
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/* CS_REC_FORMAT - register I28 */
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#define REC_FMT_reserved 0x0f /* reserved */
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#define REC_FMT_SM 0x10 /* 0: mono, 1: stereo */
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#define REC_FMT_CL 0x20 /* 0: linear, 1: companded */
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#define REC_FMT_FMT0 0x40 /* See register I8 for valid */
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#define REC_FMT_FMT1 0x80 /* combination of the FMT and CL bits */
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