2012-11-12 22:00:34 +04:00
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/* $NetBSD: pxa2x0_ac97.c,v 1.13 2012/11/12 18:00:38 skrll Exp $ */
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2005-04-13 11:42:28 +04:00
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/*
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* Copyright (c) 2003, 2005 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/select.h>
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#include <sys/audioio.h>
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2011-11-24 03:07:28 +04:00
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#include <sys/kmem.h>
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2005-04-13 11:42:28 +04:00
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#include <machine/intr.h>
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2011-07-02 00:26:35 +04:00
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#include <sys/bus.h>
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2005-04-13 11:42:28 +04:00
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#include <dev/audio_if.h>
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#include <dev/audiovar.h>
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#include <dev/mulaw.h>
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#include <dev/auconv.h>
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#include <dev/ic/ac97reg.h>
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#include <dev/ic/ac97var.h>
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2007-08-21 15:39:11 +04:00
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#include <arm/xscale/pxa2x0cpu.h>
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2005-04-13 11:42:28 +04:00
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#include <arm/xscale/pxa2x0reg.h>
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#include <arm/xscale/pxa2x0var.h>
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#include <arm/xscale/pxa2x0_gpio.h>
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#include <arm/xscale/pxa2x0_dmac.h>
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#include "locators.h"
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struct acu_dma {
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bus_dmamap_t ad_map;
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2007-03-04 08:59:00 +03:00
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void *ad_addr;
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2005-04-13 11:42:28 +04:00
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#define ACU_N_SEGS 1 /* XXX: We don't support > 1 */
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bus_dma_segment_t ad_segs[ACU_N_SEGS];
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int ad_nsegs;
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size_t ad_size;
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struct dmac_xfer *ad_dx;
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struct acu_dma *ad_next;
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};
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#define KERNADDR(ad) ((void *)((ad)->ad_addr))
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struct acu_softc {
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2011-06-09 21:29:42 +04:00
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device_t sc_dev;
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2005-04-13 11:42:28 +04:00
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bus_space_tag_t sc_bust;
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bus_dma_tag_t sc_dmat;
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bus_space_handle_t sc_bush;
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void *sc_irqcookie;
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int sc_in_reset;
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u_int sc_dac_rate;
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u_int sc_adc_rate;
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/* List of DMA ring-buffers allocated by acu_malloc() */
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struct acu_dma *sc_dmas;
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/* Dummy DMA segment which points to the AC97 PCM Fifo register */
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bus_dma_segment_t sc_dr;
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/* PCM Output (Tx) state */
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dmac_peripheral_t sc_txp;
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struct acu_dma *sc_txdma;
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void (*sc_txfunc)(void *);
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void *sc_txarg;
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/* PCM Input (Rx) state */
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dmac_peripheral_t sc_rxp;
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struct acu_dma *sc_rxdma;
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void (*sc_rxfunc)(void *);
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void *sc_rxarg;
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/* AC97 Codec State */
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struct ac97_codec_if *sc_codec_if;
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struct ac97_host_if sc_host_if;
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/* Child audio(4) device */
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2012-10-27 21:17:22 +04:00
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device_t sc_audiodev;
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2005-04-13 11:42:28 +04:00
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/* auconv encodings */
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struct audio_encoding_set *sc_encodings;
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2011-11-24 03:07:28 +04:00
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/* MPSAFE interfaces */
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kmutex_t sc_lock;
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kmutex_t sc_intr_lock;
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2005-04-13 11:42:28 +04:00
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};
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2011-06-09 21:29:42 +04:00
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static int pxaacu_match(device_t, cfdata_t, void *);
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static void pxaacu_attach(device_t, device_t, void *);
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2005-04-13 11:42:28 +04:00
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2011-06-09 21:29:42 +04:00
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CFATTACH_DECL_NEW(pxaacu, sizeof(struct acu_softc),
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2005-04-13 11:42:28 +04:00
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pxaacu_match, pxaacu_attach, NULL, NULL);
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static int acu_codec_attach(void *, struct ac97_codec_if *);
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2012-11-12 22:00:34 +04:00
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static int acu_codec_read(void *, uint8_t, uint16_t *);
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static int acu_codec_write(void *, uint8_t, uint16_t);
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2005-04-13 11:42:28 +04:00
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static int acu_codec_reset(void *);
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static int acu_intr(void *);
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static int acu_open(void *, int);
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static void acu_close(void *);
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static int acu_query_encoding(void *, struct audio_encoding *);
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static int acu_set_params(void *, int, int, audio_params_t *, audio_params_t *,
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stream_filter_list_t *, stream_filter_list_t *);
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static int acu_round_blocksize(void *, int, int, const audio_params_t *);
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static int acu_halt_output(void *);
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static int acu_halt_input(void *);
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static int acu_trigger_output(void *, void *, void *, int, void (*)(void *),
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void *, const audio_params_t *);
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static int acu_trigger_input(void *, void *, void *, int, void (*)(void *),
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void *, const audio_params_t *);
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static void acu_tx_loop_segment(struct dmac_xfer *, int);
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static void acu_rx_loop_segment(struct dmac_xfer *, int);
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static int acu_getdev(void *, struct audio_device *);
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static int acu_mixer_set_port(void *, mixer_ctrl_t *);
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static int acu_mixer_get_port(void *, mixer_ctrl_t *);
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static int acu_query_devinfo(void *, mixer_devinfo_t *);
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2011-11-24 03:07:28 +04:00
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static void *acu_malloc(void *, int, size_t);
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static void acu_free(void *, void *, size_t);
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2005-04-13 11:42:28 +04:00
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static size_t acu_round_buffersize(void *, int, size_t);
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static paddr_t acu_mappage(void *, void *, off_t, int);
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static int acu_get_props(void *);
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2011-11-24 03:07:28 +04:00
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static void acu_get_locks(void *, kmutex_t **, kmutex_t **);
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2005-04-13 11:42:28 +04:00
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struct audio_hw_if acu_hw_if = {
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acu_open,
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acu_close,
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NULL,
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acu_query_encoding,
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acu_set_params,
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acu_round_blocksize,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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acu_halt_output,
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acu_halt_input,
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NULL,
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acu_getdev,
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NULL,
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acu_mixer_set_port,
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acu_mixer_get_port,
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acu_query_devinfo,
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acu_malloc,
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acu_free,
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acu_round_buffersize,
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acu_mappage,
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acu_get_props,
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acu_trigger_output,
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acu_trigger_input,
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NULL,
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2011-11-24 03:07:28 +04:00
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acu_get_locks,
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2005-04-13 11:42:28 +04:00
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};
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struct audio_device acu_device = {
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"PXA250 AC97",
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"",
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"acu"
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};
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static const struct audio_format acu_formats[] = {
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{NULL, AUMODE_PLAY | AUMODE_RECORD, AUDIO_ENCODING_SLINEAR_LE, 16, 16,
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2, AUFMT_STEREO, 0, {4000, 48000}}
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};
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#define ACU_NFORMATS (sizeof(acu_formats) / sizeof(struct audio_format))
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2012-11-12 22:00:34 +04:00
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static inline uint32_t
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2005-04-13 11:42:28 +04:00
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acu_reg_read(struct acu_softc *sc, int reg)
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{
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return (bus_space_read_4(sc->sc_bust, sc->sc_bush, reg));
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}
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2005-12-24 23:06:46 +03:00
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static inline void
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2012-11-12 22:00:34 +04:00
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acu_reg_write(struct acu_softc *sc, int reg, uint32_t val)
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2005-04-13 11:42:28 +04:00
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{
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bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val);
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}
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2005-12-24 23:06:46 +03:00
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static inline int
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2005-04-13 11:42:28 +04:00
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acu_codec_ready(struct acu_softc *sc)
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{
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return (acu_reg_read(sc, AC97_GSR) & GSR_PCR);
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}
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2005-12-24 23:06:46 +03:00
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static inline int
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2012-11-12 22:00:34 +04:00
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acu_wait_gsr(struct acu_softc *sc, uint32_t bit)
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2005-04-13 11:42:28 +04:00
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{
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int timeout;
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2012-11-12 22:00:34 +04:00
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uint32_t rv;
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2005-04-13 11:42:28 +04:00
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for (timeout = 5000; timeout; timeout--) {
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if ((rv = acu_reg_read(sc, AC97_GSR)) & bit) {
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acu_reg_write(sc, AC97_GSR, rv | bit);
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return (0);
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}
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delay(1);
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}
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return (1);
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}
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static int
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2011-06-09 21:29:42 +04:00
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pxaacu_match(device_t parent, cfdata_t cf, void *aux)
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2005-04-13 11:42:28 +04:00
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{
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struct pxaip_attach_args *pxa = aux;
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2007-08-21 15:39:11 +04:00
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struct pxa2x0_gpioconf *gpioconf;
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u_int gpio;
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int i;
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2005-04-13 11:42:28 +04:00
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if (pxa->pxa_addr != PXA2X0_AC97_BASE ||
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pxa->pxa_intr != PXA2X0_INT_AC97)
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return (0);
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2007-08-21 15:39:11 +04:00
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gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf :
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pxa27x_pxaacu_gpioconf;
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for (i = 0; gpioconf[i].pin != -1; i++) {
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gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
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if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
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GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
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return (0);
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}
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2005-04-13 11:42:28 +04:00
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pxa->pxa_size = PXA2X0_AC97_SIZE;
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return (1);
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}
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static void
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2011-06-09 21:29:42 +04:00
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pxaacu_attach(device_t parent, device_t self, void *aux)
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2005-04-13 11:42:28 +04:00
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{
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2011-06-09 21:29:42 +04:00
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struct acu_softc *sc = device_private(self);
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2005-04-13 11:42:28 +04:00
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struct pxaip_attach_args *pxa = aux;
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2011-06-09 21:29:42 +04:00
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sc->sc_dev = self;
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2005-04-13 11:42:28 +04:00
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sc->sc_bust = pxa->pxa_iot;
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sc->sc_dmat = pxa->pxa_dmat;
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aprint_naive("\n");
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aprint_normal(": AC97 Controller\n");
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if (bus_space_map(sc->sc_bust, pxa->pxa_addr, pxa->pxa_size, 0,
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&sc->sc_bush)) {
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2011-06-09 21:29:42 +04:00
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aprint_error_dev(self, "Can't map registers!\n");
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2005-04-13 11:42:28 +04:00
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return;
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}
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2011-11-24 07:35:56 +04:00
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sc->sc_irqcookie = pxa2x0_intr_establish(pxa->pxa_intr, IPL_AUDIO,
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2005-04-13 11:42:28 +04:00
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acu_intr, sc);
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KASSERT(sc->sc_irqcookie != NULL);
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/* Make sure the AC97 clock is enabled */
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2007-02-22 08:14:04 +03:00
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pxa2x0_clkman_config(CKEN_AC97, true);
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2005-04-13 11:42:28 +04:00
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delay(100);
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/* Do a cold reset */
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acu_reg_write(sc, AC97_GCR, 0);
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delay(100);
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acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
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delay(100);
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acu_reg_write(sc, AC97_CAR, 0);
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if (acu_wait_gsr(sc, GSR_PCR)) {
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acu_reg_write(sc, AC97_GCR, 0);
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delay(100);
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2007-02-22 08:14:04 +03:00
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pxa2x0_clkman_config(CKEN_AC97, false);
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2005-04-13 11:42:28 +04:00
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bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
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2011-06-09 21:29:42 +04:00
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aprint_error_dev(self, "Primary codec not ready\n");
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2005-04-13 11:42:28 +04:00
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return;
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}
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sc->sc_dr.ds_addr = pxa->pxa_addr + AC97_PCDR;
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|
|
sc->sc_dr.ds_len = 4;
|
|
|
|
|
|
|
|
sc->sc_codec_if = NULL;
|
|
|
|
sc->sc_host_if.arg = sc;
|
|
|
|
sc->sc_host_if.attach = acu_codec_attach;
|
|
|
|
sc->sc_host_if.read = acu_codec_read;
|
|
|
|
sc->sc_host_if.write = acu_codec_write;
|
|
|
|
sc->sc_host_if.reset = acu_codec_reset;
|
|
|
|
sc->sc_host_if.flags = NULL;
|
|
|
|
sc->sc_in_reset = 0;
|
|
|
|
sc->sc_dac_rate = sc->sc_adc_rate = 0;
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
if (ac97_attach(&sc->sc_host_if, sc->sc_dev, &sc->sc_lock)) {
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(self, "Failed to attach primary codec\n");
|
2005-04-13 11:42:28 +04:00
|
|
|
fail:
|
|
|
|
acu_reg_write(sc, AC97_GCR, 0);
|
|
|
|
delay(100);
|
2007-02-22 08:14:04 +03:00
|
|
|
pxa2x0_clkman_config(CKEN_AC97, false);
|
2005-04-13 11:42:28 +04:00
|
|
|
bus_space_unmap(sc->sc_bust, sc->sc_bush, pxa->pxa_size);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (auconv_create_encodings(acu_formats, ACU_NFORMATS,
|
|
|
|
&sc->sc_encodings)) {
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(self, "Failed to create encodings\n");
|
2005-04-13 11:42:28 +04:00
|
|
|
if (sc->sc_codec_if != NULL)
|
|
|
|
(sc->sc_codec_if->vtbl->detach)(sc->sc_codec_if);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
2011-06-09 21:29:42 +04:00
|
|
|
sc->sc_audiodev = audio_attach_mi(&acu_hw_if, sc, sc->sc_dev);
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* As a work-around for braindamage in the PXA250's AC97 controller
|
|
|
|
* (see errata #125), we hold the ACUNIT/Codec in Cold Reset until
|
|
|
|
* acu_open() is called. acu_close() also puts the controller into
|
|
|
|
* Cold Reset.
|
|
|
|
*
|
|
|
|
* While this won't necessarily prevent Rx FIFO overruns, it at least
|
|
|
|
* allows the user to recover by closing then re-opening the audio
|
|
|
|
* device.
|
|
|
|
*/
|
|
|
|
acu_reg_write(sc, AC97_GCR, 0);
|
|
|
|
sc->sc_in_reset = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_codec_attach(void *arg, struct ac97_codec_if *aci)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
sc->sc_codec_if = aci;
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2012-11-12 22:00:34 +04:00
|
|
|
acu_codec_read(void *arg, uint8_t codec_reg, uint16_t *valp)
|
2005-04-13 11:42:28 +04:00
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
2012-11-12 22:00:34 +04:00
|
|
|
uint32_t val;
|
2011-11-24 03:07:28 +04:00
|
|
|
int reg, rv = 1;
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we're currently closed, return non-zero. The ac97 frontend
|
|
|
|
* will use its cached copy of the register instead.
|
|
|
|
*/
|
|
|
|
if (sc->sc_in_reset)
|
|
|
|
return (1);
|
|
|
|
|
|
|
|
reg = AC97_CODEC_BASE(0) + codec_reg * 2;
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP))
|
|
|
|
goto out_nocar;
|
|
|
|
|
|
|
|
val = acu_reg_read(sc, AC97_GSR);
|
|
|
|
val |= GSR_RDCS | GSR_SDONE;
|
|
|
|
acu_reg_write(sc, AC97_GSR, val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Dummy read to initiate the real read access
|
|
|
|
*/
|
|
|
|
(void) acu_reg_read(sc, reg);
|
|
|
|
if (acu_wait_gsr(sc, GSR_SDONE))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
(void) acu_reg_read(sc, reg);
|
|
|
|
if (acu_wait_gsr(sc, GSR_SDONE))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
val = acu_reg_read(sc, AC97_GSR);
|
|
|
|
if (val & GSR_RDCS)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
*valp = acu_reg_read(sc, reg);
|
|
|
|
if (acu_wait_gsr(sc, GSR_SDONE))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
rv = 0;
|
|
|
|
|
|
|
|
out:
|
|
|
|
acu_reg_write(sc, AC97_CAR, 0);
|
|
|
|
out_nocar:
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
delay(10);
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2012-11-12 22:00:34 +04:00
|
|
|
acu_codec_write(void *arg, uint8_t codec_reg, uint16_t val)
|
2005-04-13 11:42:28 +04:00
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
2012-11-12 22:00:34 +04:00
|
|
|
uint16_t rv;
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we're currently closed, chances are the user is just
|
|
|
|
* tweaking mixer settings. Pretend the write succeeded.
|
|
|
|
* The ac97 frontend will cache the value anyway, and it'll
|
|
|
|
* be written correctly when the driver is opened.
|
|
|
|
*/
|
|
|
|
if (sc->sc_in_reset)
|
|
|
|
return (0);
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
if (!acu_codec_ready(sc) || (acu_reg_read(sc, AC97_CAR) & CAR_CAIP)) {
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
rv = acu_reg_read(sc, AC97_GSR);
|
|
|
|
rv |= GSR_RDCS | GSR_CDONE;
|
|
|
|
acu_reg_write(sc, AC97_GSR, rv);
|
|
|
|
|
|
|
|
acu_reg_write(sc, AC97_CODEC_BASE(0) + codec_reg * 2, val);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for the write to complete
|
|
|
|
*/
|
|
|
|
(void) acu_wait_gsr(sc, GSR_CDONE);
|
|
|
|
acu_reg_write(sc, AC97_CAR, 0);
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
delay(10);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_codec_reset(void *arg)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
2012-11-12 22:00:34 +04:00
|
|
|
uint32_t rv;
|
2005-04-13 11:42:28 +04:00
|
|
|
|
|
|
|
rv = acu_reg_read(sc, AC97_GCR);
|
|
|
|
acu_reg_write(sc, AC97_GCR, rv | GCR_WARM_RST);
|
|
|
|
delay(100);
|
|
|
|
acu_reg_write(sc, AC97_GCR, rv);
|
|
|
|
delay(100);
|
|
|
|
|
|
|
|
if (acu_wait_gsr(sc, GSR_PCR)) {
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(sc->sc_dev,
|
|
|
|
"acu_codec_reset: failed to ready after reset\n");
|
2005-04-13 11:42:28 +04:00
|
|
|
return (ETIMEDOUT);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_intr(void *arg)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
2012-11-12 22:00:34 +04:00
|
|
|
uint32_t gsr, reg;
|
2005-04-13 11:42:28 +04:00
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
gsr = acu_reg_read(sc, AC97_GSR);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Tx FIFO underruns are no big deal. Just log it and ignore and
|
|
|
|
* subsequent underruns until the next time acu_trigger_output()
|
|
|
|
* is called.
|
|
|
|
*/
|
|
|
|
if ((gsr & GSR_POINT) && (acu_reg_read(sc, AC97_POCR) & AC97_FEFIE)) {
|
|
|
|
acu_reg_write(sc, AC97_POCR, 0);
|
|
|
|
reg = acu_reg_read(sc, AC97_POSR);
|
|
|
|
acu_reg_write(sc, AC97_POSR, reg);
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(sc->sc_dev, "Tx PCM Fifo underrun\n");
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Rx FIFO overruns are a different story. See PAX250 Errata #125
|
|
|
|
* for the gory details.
|
|
|
|
* I don't see any way to gracefully recover from this problem,
|
|
|
|
* other than a issuing a Cold Reset in acu_close().
|
|
|
|
* The best we can do here is to report the problem on the console.
|
|
|
|
*/
|
|
|
|
if ((gsr & GSR_PIINT) && (acu_reg_read(sc, AC97_PICR) & AC97_FEFIE)) {
|
|
|
|
acu_reg_write(sc, AC97_PICR, 0);
|
|
|
|
reg = acu_reg_read(sc, AC97_PISR);
|
|
|
|
acu_reg_write(sc, AC97_PISR, reg);
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(sc->sc_dev, "Rx PCM Fifo overrun\n");
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
|
|
|
|
2005-04-13 11:42:28 +04:00
|
|
|
return (1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_open(void *arg, int flags)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Deassert Cold Reset
|
|
|
|
*/
|
|
|
|
acu_reg_write(sc, AC97_GCR, GCR_COLD_RST);
|
|
|
|
delay(100);
|
|
|
|
acu_reg_write(sc, AC97_CAR, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Wait for the primary codec to become ready
|
|
|
|
*/
|
|
|
|
if (acu_wait_gsr(sc, GSR_PCR))
|
|
|
|
return (EIO);
|
|
|
|
sc->sc_in_reset = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Restore the codec port settings
|
|
|
|
*/
|
|
|
|
sc->sc_codec_if->vtbl->restore_ports(sc->sc_codec_if);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Need to reprogram the sample rates, since 'restore_ports'
|
|
|
|
* doesn't do it.
|
|
|
|
*
|
|
|
|
* XXX: These aren't the only two sample rate registers ...
|
|
|
|
*/
|
|
|
|
if (sc->sc_dac_rate)
|
|
|
|
(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
|
|
|
|
AC97_REG_PCM_FRONT_DAC_RATE, &sc->sc_dac_rate);
|
|
|
|
if (sc->sc_adc_rate)
|
|
|
|
(void) sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
|
|
|
|
AC97_REG_PCM_LR_ADC_RATE, &sc->sc_adc_rate);
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
acu_close(void *arg)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Make sure the hardware is quiescent
|
|
|
|
*/
|
|
|
|
acu_halt_output(sc);
|
|
|
|
acu_halt_input(sc);
|
|
|
|
delay(100);
|
|
|
|
|
|
|
|
/* Assert Cold Reset */
|
|
|
|
acu_reg_write(sc, AC97_GCR, 0);
|
|
|
|
sc->sc_in_reset = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_query_encoding(void *arg, struct audio_encoding *fp)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
return (auconv_query_encoding(sc->sc_encodings, fp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_set_params(void *arg, int setmode, int usemode,
|
|
|
|
audio_params_t *play, audio_params_t *rec,
|
|
|
|
stream_filter_list_t *pfil, stream_filter_list_t *rfil)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct audio_params *p;
|
|
|
|
stream_filter_list_t *fil;
|
|
|
|
int mode, err;
|
|
|
|
|
|
|
|
for (mode = AUMODE_RECORD; mode != -1;
|
|
|
|
mode = (mode == AUMODE_RECORD) ? AUMODE_PLAY : -1) {
|
|
|
|
if ((setmode & mode) == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
p = (mode == AUMODE_PLAY) ? play : rec;
|
|
|
|
|
|
|
|
if (p->sample_rate < 4000 || p->sample_rate > 48000 ||
|
|
|
|
(p->precision != 8 && p->precision != 16) ||
|
|
|
|
(p->channels != 1 && p->channels != 2)) {
|
|
|
|
printf("acu_set_params: precision/channels botch\n");
|
|
|
|
printf("acu_set_params: rate %d, prec %d, chan %d\n",
|
|
|
|
p->sample_rate, p->precision, p->channels);
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
fil = (mode == AUMODE_PLAY) ? pfil : rfil;
|
|
|
|
err = auconv_set_converter(acu_formats, ACU_NFORMATS,
|
2007-02-22 08:14:04 +03:00
|
|
|
mode, p, true, fil);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (err < 0)
|
|
|
|
return (EINVAL);
|
|
|
|
|
|
|
|
if (mode == AUMODE_PLAY) {
|
|
|
|
err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
|
|
|
|
AC97_REG_PCM_FRONT_DAC_RATE, &play->sample_rate);
|
|
|
|
sc->sc_dac_rate = play->sample_rate;
|
|
|
|
} else {
|
|
|
|
err = sc->sc_codec_if->vtbl->set_rate(sc->sc_codec_if,
|
|
|
|
AC97_REG_PCM_LR_ADC_RATE, &rec->sample_rate);
|
|
|
|
sc->sc_adc_rate = rec->sample_rate;
|
|
|
|
}
|
|
|
|
if (err)
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_round_blocksize(void *arg, int blk, int mode, const audio_params_t *param)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (blk & ~0x1f);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_getdev(void *addr, struct audio_device *retp)
|
|
|
|
{
|
|
|
|
|
|
|
|
*retp = acu_device;
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_mixer_set_port(void *arg, mixer_ctrl_t *cp)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
return (sc->sc_codec_if->vtbl->mixer_set_port(sc->sc_codec_if, cp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_mixer_get_port(void *arg, mixer_ctrl_t *cp)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
return (sc->sc_codec_if->vtbl->mixer_get_port(sc->sc_codec_if, cp));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_query_devinfo(void *arg, mixer_devinfo_t *dip)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
|
|
|
return (sc->sc_codec_if->vtbl->query_devinfo(sc->sc_codec_if, dip));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void *
|
2011-11-24 03:07:28 +04:00
|
|
|
acu_malloc(void *arg, int direction, size_t size)
|
2005-04-13 11:42:28 +04:00
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
int error;
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
if ((ad = kmem_alloc(sizeof(*ad), KM_SLEEP)) == NULL)
|
2005-04-13 11:42:28 +04:00
|
|
|
return (NULL);
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
/* XXX */
|
|
|
|
if ((ad->ad_dx = pxa2x0_dmac_allocate_xfer()) == NULL)
|
2005-04-13 11:42:28 +04:00
|
|
|
goto error;
|
|
|
|
|
|
|
|
ad->ad_size = size;
|
|
|
|
|
|
|
|
error = bus_dmamem_alloc(sc->sc_dmat, size, 16, 0, ad->ad_segs,
|
2011-11-24 03:07:28 +04:00
|
|
|
ACU_N_SEGS, &ad->ad_nsegs, BUS_DMA_WAITOK);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (error)
|
|
|
|
goto free_xfer;
|
|
|
|
|
|
|
|
error = bus_dmamem_map(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs, size,
|
2011-11-24 03:07:28 +04:00
|
|
|
&ad->ad_addr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_NOCACHE);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (error)
|
|
|
|
goto free_dmamem;
|
|
|
|
|
|
|
|
error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
|
2011-11-24 03:07:28 +04:00
|
|
|
BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &ad->ad_map);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (error)
|
|
|
|
goto unmap_dmamem;
|
|
|
|
|
|
|
|
error = bus_dmamap_load(sc->sc_dmat, ad->ad_map, ad->ad_addr, size,
|
2011-11-24 03:07:28 +04:00
|
|
|
NULL, BUS_DMA_WAITOK);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (error) {
|
|
|
|
bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
|
|
|
|
unmap_dmamem: bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, size);
|
|
|
|
free_dmamem: bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
|
|
|
|
free_xfer: pxa2x0_dmac_free_xfer(ad->ad_dx);
|
2011-11-24 03:07:28 +04:00
|
|
|
error: kmem_free(ad, sizeof(*ad));
|
2005-04-13 11:42:28 +04:00
|
|
|
return (NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
ad->ad_dx->dx_cookie = sc;
|
|
|
|
ad->ad_dx->dx_priority = DMAC_PRIORITY_HIGH;
|
|
|
|
ad->ad_dx->dx_dev_width = DMAC_DEV_WIDTH_4;
|
|
|
|
ad->ad_dx->dx_burst_size = DMAC_BURST_SIZE_32;
|
|
|
|
|
|
|
|
ad->ad_next = sc->sc_dmas;
|
|
|
|
sc->sc_dmas = ad;
|
|
|
|
return (KERNADDR(ad));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2011-11-24 03:07:28 +04:00
|
|
|
acu_free(void *arg, void *ptr, size_t size)
|
2005-04-13 11:42:28 +04:00
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct acu_dma *ad, **adp;
|
|
|
|
|
|
|
|
for (adp = &sc->sc_dmas; (ad = *adp) != NULL; adp = &ad->ad_next) {
|
|
|
|
if (KERNADDR(ad) == ptr) {
|
|
|
|
pxa2x0_dmac_abort_xfer(ad->ad_dx);
|
|
|
|
pxa2x0_dmac_free_xfer(ad->ad_dx);
|
|
|
|
ad->ad_segs[0].ds_len = ad->ad_size; /* XXX */
|
|
|
|
bus_dmamap_unload(sc->sc_dmat, ad->ad_map);
|
|
|
|
bus_dmamap_destroy(sc->sc_dmat, ad->ad_map);
|
|
|
|
bus_dmamem_unmap(sc->sc_dmat, ad->ad_addr, ad->ad_size);
|
|
|
|
bus_dmamem_free(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs);
|
|
|
|
*adp = ad->ad_next;
|
2011-11-24 03:07:28 +04:00
|
|
|
kmem_free(ad, sizeof(*ad));
|
2005-04-13 11:42:28 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t
|
|
|
|
acu_round_buffersize(void *arg, int direction, size_t size)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static paddr_t
|
|
|
|
acu_mappage(void *arg, void *mem, off_t off, int prot)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
|
|
|
|
if (off < 0)
|
|
|
|
return (-1);
|
|
|
|
for (ad = sc->sc_dmas; ad && KERNADDR(ad) != mem; ad = ad->ad_next)
|
|
|
|
;
|
|
|
|
if (ad == NULL)
|
|
|
|
return (-1);
|
|
|
|
return (bus_dmamem_mmap(sc->sc_dmat, ad->ad_segs, ad->ad_nsegs,
|
|
|
|
off, prot, BUS_DMA_WAITOK));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_get_props(void *arg)
|
|
|
|
{
|
|
|
|
|
|
|
|
return (AUDIO_PROP_MMAP|AUDIO_PROP_INDEPENDENT|AUDIO_PROP_FULLDUPLEX);
|
|
|
|
}
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
static void
|
|
|
|
acu_get_locks(void *opaque, kmutex_t **intr, kmutex_t **thread)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = opaque;
|
|
|
|
|
|
|
|
*intr = &sc->sc_intr_lock;
|
|
|
|
*thread = &sc->sc_lock;
|
|
|
|
}
|
|
|
|
|
2005-04-13 11:42:28 +04:00
|
|
|
static int
|
|
|
|
acu_halt_output(void *arg)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (sc->sc_txdma) {
|
|
|
|
acu_reg_write(sc, AC97_POCR, 0);
|
|
|
|
acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
|
|
|
|
pxa2x0_dmac_abort_xfer(sc->sc_txdma->ad_dx);
|
|
|
|
sc->sc_txdma = NULL;
|
|
|
|
}
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_halt_input(void *arg)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
if (sc->sc_rxdma) {
|
|
|
|
acu_reg_write(sc, AC97_PICR, 0);
|
|
|
|
acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
|
|
|
|
pxa2x0_dmac_abort_xfer(sc->sc_rxdma->ad_dx);
|
|
|
|
sc->sc_rxdma = NULL;
|
|
|
|
}
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_trigger_output(void *arg, void *start, void *end, int blksize,
|
|
|
|
void (*tx_func)(void *), void *tx_arg, const audio_params_t *param)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct dmac_xfer *dx;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
if (sc->sc_txdma)
|
|
|
|
return (EBUSY);
|
|
|
|
|
|
|
|
sc->sc_txfunc = tx_func;
|
|
|
|
sc->sc_txarg = tx_arg;
|
|
|
|
|
|
|
|
for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
|
|
|
|
;
|
|
|
|
if (ad == NULL) {
|
|
|
|
printf("acu_trigger_output: bad addr %p\n", start);
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->sc_txdma = ad;
|
|
|
|
ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
|
|
|
|
ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fix up a looping DMA request.
|
|
|
|
* The 'done' function will be called for every 'blksize' bytes
|
|
|
|
* transferred by the DMA engine.
|
|
|
|
*/
|
|
|
|
dx = ad->ad_dx;
|
|
|
|
dx->dx_done = acu_tx_loop_segment;
|
|
|
|
dx->dx_peripheral = DMAC_PERIPH_AC97AUDIOTX;
|
|
|
|
dx->dx_flow = DMAC_FLOW_CTRL_DEST;
|
|
|
|
dx->dx_loop_notify = blksize;
|
2007-02-22 08:14:04 +03:00
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = false;
|
2005-04-13 11:42:28 +04:00
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = ad->ad_nsegs;
|
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = ad->ad_segs;
|
2007-02-22 08:14:04 +03:00
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = true;
|
2005-04-13 11:42:28 +04:00
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_nsegs = 1;
|
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = &sc->sc_dr;
|
|
|
|
|
|
|
|
rv = pxa2x0_dmac_start_xfer(dx);
|
|
|
|
if (rv == 0) {
|
|
|
|
/*
|
|
|
|
* XXX: We should only do this once the request has been
|
|
|
|
* loaded into a DMAC channel.
|
|
|
|
*/
|
|
|
|
acu_reg_write(sc, AC97_POSR, AC97_FIFOE);
|
|
|
|
acu_reg_write(sc, AC97_POCR, AC97_FEFIE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
acu_trigger_input(void *arg, void *start, void *end, int blksize,
|
|
|
|
void (*rx_func)(void *), void *rx_arg, const audio_params_t *param)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = arg;
|
|
|
|
struct dmac_xfer *dx;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
int rv;
|
|
|
|
|
|
|
|
if (sc->sc_rxdma)
|
|
|
|
return (EBUSY);
|
|
|
|
|
|
|
|
sc->sc_rxfunc = rx_func;
|
|
|
|
sc->sc_rxarg = rx_arg;
|
|
|
|
|
|
|
|
for (ad = sc->sc_dmas; ad && KERNADDR(ad) != start; ad = ad->ad_next)
|
|
|
|
;
|
|
|
|
if (ad == NULL) {
|
|
|
|
printf("acu_trigger_input: bad addr %p\n", start);
|
|
|
|
return (EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
sc->sc_rxdma = ad;
|
|
|
|
ad->ad_segs[0].ds_addr = ad->ad_map->dm_segs[0].ds_addr;
|
|
|
|
ad->ad_segs[0].ds_len = (uintptr_t)end - (uintptr_t)start;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Fix up a looping DMA request.
|
|
|
|
* The 'done' function will be called for every 'blksize' bytes
|
|
|
|
* transferred by the DMA engine.
|
|
|
|
*/
|
|
|
|
dx = ad->ad_dx;
|
|
|
|
dx->dx_done = acu_rx_loop_segment;
|
|
|
|
dx->dx_peripheral = DMAC_PERIPH_AC97AUDIORX;
|
|
|
|
dx->dx_flow = DMAC_FLOW_CTRL_SRC;
|
|
|
|
dx->dx_loop_notify = blksize;
|
2007-02-22 08:14:04 +03:00
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_addr_hold = false;
|
2005-04-13 11:42:28 +04:00
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_nsegs = ad->ad_nsegs;
|
|
|
|
dx->dx_desc[DMAC_DESC_DST].xd_dma_segs = ad->ad_segs;
|
2007-02-22 08:14:04 +03:00
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_addr_hold = true;
|
2005-04-13 11:42:28 +04:00
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_nsegs = 1;
|
|
|
|
dx->dx_desc[DMAC_DESC_SRC].xd_dma_segs = &sc->sc_dr;
|
|
|
|
|
|
|
|
rv = pxa2x0_dmac_start_xfer(dx);
|
|
|
|
|
|
|
|
if (rv == 0) {
|
|
|
|
/*
|
|
|
|
* XXX: We should only do this once the request has been
|
|
|
|
* loaded into a DMAC channel.
|
|
|
|
*/
|
|
|
|
acu_reg_write(sc, AC97_PISR, AC97_FIFOE);
|
|
|
|
acu_reg_write(sc, AC97_PICR, AC97_FEFIE);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (rv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
acu_tx_loop_segment(struct dmac_xfer *dx, int status)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = dx->dx_cookie;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
|
|
|
|
if ((ad = sc->sc_txdma) == NULL)
|
|
|
|
panic("acu_tx_loop_segment: bad TX dma descriptor!");
|
|
|
|
|
|
|
|
if (ad->ad_dx != dx)
|
|
|
|
panic("acu_tx_loop_segment: xfer mismatch!");
|
|
|
|
|
|
|
|
if (status) {
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(sc->sc_dev,
|
|
|
|
"acu_tx_loop_segment: non-zero completion status %d\n",
|
|
|
|
status);
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
(sc->sc_txfunc)(sc->sc_txarg);
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
acu_rx_loop_segment(struct dmac_xfer *dx, int status)
|
|
|
|
{
|
|
|
|
struct acu_softc *sc = dx->dx_cookie;
|
|
|
|
struct acu_dma *ad;
|
|
|
|
|
|
|
|
if ((ad = sc->sc_rxdma) == NULL)
|
|
|
|
panic("acu_rx_loop_segment: bad RX dma descriptor!");
|
|
|
|
|
|
|
|
if (ad->ad_dx != dx)
|
|
|
|
panic("acu_rx_loop_segment: xfer mismatch!");
|
|
|
|
|
|
|
|
if (status) {
|
2011-06-09 21:29:42 +04:00
|
|
|
aprint_error_dev(sc->sc_dev,
|
|
|
|
"acu_rx_loop_segment: non-zero completion status %d\n",
|
|
|
|
status);
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|
|
|
|
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
(sc->sc_rxfunc)(sc->sc_rxarg);
|
2011-11-24 03:07:28 +04:00
|
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
2005-04-13 11:42:28 +04:00
|
|
|
}
|