2001-01-05 15:49:52 +03:00
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/*
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2005-02-27 03:26:58 +03:00
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* Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved.
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2001-01-05 15:49:52 +03:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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* 4. Altered versions must be plainly marked as such, and must not be
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* misrepresented as being the original software and/or documentation.
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2005-02-27 03:26:58 +03:00
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*
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2001-01-05 15:49:52 +03:00
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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2005-12-11 15:16:03 +03:00
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* $Id: isac.h,v 1.3 2005/12/11 12:21:27 christos Exp $
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2001-01-05 15:49:52 +03:00
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*
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* last edit-date: [Sun Feb 14 10:27:13 1999]
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*
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* -hm split up for rewrite of Siemens chipset driver
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*
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*---------------------------------------------------------------------------
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*/
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2005-02-27 03:26:58 +03:00
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2001-01-05 15:49:52 +03:00
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#ifndef I4B_ISAC_H_
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#define I4B_ISAC_H_
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/*
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* The ISAC databook specifies a delay of 2.5 DCL clock cycles between
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* writes to the ISAC command register CMDR. This is the delay used to
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* satisfy this requirement.
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*/
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#define I4B_ISAC_CMDRWRDELAY 30
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#if (I4B_ISAC_CMDRWRDELAY > 0)
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#define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY)
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#else
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#warning "I4B_ISAC_CMDRWRDELAY set to 0!"
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#define ISACCMDRWRDELAY()
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#endif
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2005-02-27 03:26:58 +03:00
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2001-01-05 15:49:52 +03:00
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enum ISAC_VERSIONS {
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ISAC_VA, /* 2085 A1 or A2, 2086/2186 V1.1 */
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ISAC_VB1, /* 2085 B1 */
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ISAC_VB2, /* 2085 B2 */
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ISAC_VB3, /* 2085 B3/V2.3 */
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ISAC_UNKN /* unknown version */
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};
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#define ISAC_FIFO_LEN 32 /* 32 bytes FIFO on chip */
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/*
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* definitions of registers and bits for the ISAC ISDN chip.
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*/
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2005-02-27 03:26:58 +03:00
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2001-01-05 15:49:52 +03:00
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typedef struct isac_reg {
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/* 32 byte deep FIFO always first */
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unsigned char isac_fifo [ISAC_FIFO_LEN];
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/* most registers can be read/written, but have different names */
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/* so define a union with read/write names to make that clear */
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union {
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struct {
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unsigned char isac_ista;
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unsigned char isac_star;
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unsigned char isac_mode;
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unsigned char isac_timr;
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unsigned char isac_exir;
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unsigned char isac_rbcl;
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unsigned char isac_sapr;
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unsigned char isac_rsta;
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unsigned char dummy_28;
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unsigned char isac_rhcr;
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unsigned char isac_rbch;
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unsigned char isac_star2;
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unsigned char dummy_2c;
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unsigned char dummy_2d;
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unsigned char dummy_2e;
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unsigned char dummt_2f;
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unsigned char isac_spcr;
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unsigned char isac_cirr;
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unsigned char isac_mor;
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unsigned char isac_sscr;
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unsigned char isac_sfcr;
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unsigned char isac_c1r;
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unsigned char isac_c2r;
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unsigned char isac_b1cr;
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unsigned char isac_b2cr;
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unsigned char isac_adf2;
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unsigned char isac_mosr;
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unsigned char isac_sqrr;
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} isac_r;
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struct {
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unsigned char isac_mask;
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unsigned char isac_cmdr;
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unsigned char isac_mode;
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unsigned char isac_timr;
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unsigned char isac_xad1;
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unsigned char isac_xad2;
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unsigned char isac_sap1;
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unsigned char isac_sap2;
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unsigned char isac_tei1;
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unsigned char isac_tei2;
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unsigned char dummy_2a;
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unsigned char isac_star2;
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unsigned char dummy_2c;
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unsigned char dummy_2d;
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unsigned char dummy_2e;
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unsigned char dummt_2f;
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unsigned char isac_spcr;
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unsigned char isac_cixr;
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unsigned char isac_mox;
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unsigned char isac_sscx;
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unsigned char isac_sfcw;
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unsigned char isac_c1r;
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unsigned char isac_c2r;
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unsigned char isac_stcr;
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unsigned char isac_adf1;
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unsigned char isac_adf2;
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unsigned char isac_mocr;
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unsigned char isac_sqxr;
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} isac_w;
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} isac_rw;
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} isac_reg_t;
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#define REG_OFFSET(type, field) (int)(&(((type *)0)->field))
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/* ISAC read registers */
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#define i_ista isac_rw.isac_r.isac_ista
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#define I_ISTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_ista)
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#define i_star isac_rw.isac_r.isac_star
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#define I_STAR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star)
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#define i_mode isac_rw.isac_r.isac_mode
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#define I_MODE REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mode)
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#define i_timr isac_rw.isac_r.isac_timr
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#define I_TIMR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_timr)
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#define i_exir isac_rw.isac_r.isac_exir
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#define I_EXIR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_exir)
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#define i_rbcl isac_rw.isac_r.isac_rbcl
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#define I_RBCL REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbcl)
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#define i_sapr isac_rw.isac_r.isac_sapr
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#define I_SAPR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sapr)
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#define i_rsta isac_rw.isac_r.isac_rsta
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#define I_RSTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rsta)
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#define i_rhcr isac_rw.isac_r.isac_rhcr
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#define I_RHCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rhcr)
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#define i_rbch isac_rw.isac_r.isac_rbch
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#define I_RBCH REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbch)
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#define i_star2 isac_rw.isac_r.isac_star2
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#define I_STAR2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star2)
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#define i_spcr isac_rw.isac_r.isac_spcr
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#define I_SPCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_spcr)
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#define i_cirr isac_rw.isac_r.isac_cirr
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#define I_CIRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_cirr)
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#define i_mor isac_rw.isac_r.isac_mor
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#define I_MOR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mor)
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#define i_sscr isac_rw.isac_r.isac_sscr
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#define I_SSCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sscr)
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#define i_sfcr isac_rw.isac_r.isac_sfcr
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#define I_SFCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sfcr)
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#define i_c1r isac_rw.isac_r.isac_c1r
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#define I_C1R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c1r)
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#define i_c2r isac_rw.isac_r.isac_c2r
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#define I_C2R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c2r)
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#define i_b1cr isac_rw.isac_r.isac_b1cr
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#define I_B1CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b1cr)
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#define i_b2cr isac_rw.isac_r.isac_b2cr
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#define I_B2CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b2cr)
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#define i_adf2 isac_rw.isac_r.isac_adf2
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#define I_ADF2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_adf2)
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#define i_mosr isac_rw.isac_r.isac_mosr
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#define I_MOSR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mosr)
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#define i_sqrr isac_rw.isac_r.isac_sqrr
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#define I_SQRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sqrr)
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/* ISAC write registers - isac_mode, isac_timr, isac_star2, isac_spcr, */
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/* isac_c1r, isac_c2r, isac_adf2 see read registers */
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#define i_mask isac_rw.isac_w.isac_mask
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#define I_MASK REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mask)
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#define i_cmdr isac_rw.isac_w.isac_cmdr
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#define I_CMDR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cmdr)
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#define i_xad1 isac_rw.isac_w.isac_xad1
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#define I_XAD1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad1)
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#define i_xad2 isac_rw.isac_w.isac_xad2
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#define I_XAD2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad2)
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#define i_sap1 isac_rw.isac_w.isac_sap1
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#define I_SAP1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap1)
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#define i_sap2 isac_rw.isac_w.isac_sap2
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#define I_SAP2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap2)
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#define i_tei1 isac_rw.isac_w.isac_tei1
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#define i_tei2 isac_rw.isac_w.isac_tei2
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#define i_cixr isac_rw.isac_w.isac_cixr
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#define I_CIXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cixr)
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#define I_CIX0 I_CIXR
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#define i_mox isac_rw.isac_w.isac_mox
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#define I_MOX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mox)
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#define i_sscx isac_rw.isac_w.isac_sscx
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#define I_SSCX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sscx)
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#define i_sfcw isac_rw.isac_w.isac_sfcw
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#define I_SFCW REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sfcw)
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#define i_stcr isac_rw.isac_w.isac_stcr
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#define I_STCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_stcr)
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#define i_adf1 isac_rw.isac_w.isac_adf1
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#define I_ADF1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_adf1)
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#define i_mocr isac_rw.isac_w.isac_mocr
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#define I_MOCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mocr)
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#define i_sqxr isac_rw.isac_w.isac_sqxr
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#define I_SQXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sqxr)
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#define ISAC_ISTA_RME 0x80
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#define ISAC_ISTA_RPF 0x40
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#define ISAC_ISTA_RSC 0x20
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#define ISAC_ISTA_XPR 0x10
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#define ISAC_ISTA_TIN 0x08
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#define ISAC_ISTA_CISQ 0x04
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#define ISAC_ISTA_SIN 0x02
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#define ISAC_ISTA_EXI 0x01
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#define ISAC_MASK_RME 0x80
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#define ISAC_MASL_RPF 0x40
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#define ISAC_MASK_RSC 0x20
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#define ISAC_MASK_XPR 0x10
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#define ISAC_MASK_TIN 0x08
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#define ISAC_MASK_CISQ 0x04
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#define ISAC_MASK_SIN 0x02
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#define ISAC_MASK_EXI 0x01
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#define ISAC_MASK_ALL 0xff
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#define ISAC_STAR_XDOV 0x80
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#define ISAC_STAR_XFW 0x40
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#define ISAC_STAR_XRNR 0x20
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#define ISAC_STAR_RRNR 0x10
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#define ISAC_STAR_MBR 0x08
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#define ISAC_STAR_MAC1 0x04
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#define ISAC_STAR_BVS 0x02
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#define ISAC_STAR_MAC0 0x01
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#define ISAC_CMDR_RMC 0x80
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#define ISAC_CMDR_RRES 0x40
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#define ISAC_CMDR_RNR 0x20
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#define ISAC_CMDR_STI 0x10
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#define ISAC_CMDR_XTF 0x08
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#define ISAC_CMDR_XIF 0x04
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#define ISAC_CMDR_XME 0x02
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#define ISAC_CMDR_XRES 0x01
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#define ISAC_MODE_MDS2 0x80
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#define ISAC_MODE_MDS1 0x40
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#define ISAC_MODE_MDS0 0x20
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#define ISAC_MODE_TMD 0x10
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#define ISAC_MODE_RAC 0x08
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#define ISAC_MODE_DIM2 0x04
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#define ISAC_MODE_DIM1 0x02
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#define ISAC_MODE_DIM0 0x01
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#define ISAC_EXIR_XMR 0x80
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#define ISAC_EXIR_XDU 0x40
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#define ISAC_EXIR_PCE 0x20
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#define ISAC_EXIR_RFO 0x10
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#define ISAC_EXIR_SOV 0x08
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#define ISAC_EXIR_MOS 0x04
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#define ISAC_EXIR_SAW 0x02
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#define ISAC_EXIR_WOV 0x01
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#define ISAC_RSTA_RDA 0x80
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#define ISAC_RSTA_RDO 0x40
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#define ISAC_RSTA_CRC 0x20
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#define ISAC_RSTA_RAB 0x10
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#define ISAC_RSTA_SA1 0x08
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#define ISAC_RSTA_SA0 0x04
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#define ISAC_RSTA_CR 0x02
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#define ISAC_RSTA_TA 0x01
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#define ISAC_RSTA_MASK 0x70 /* the interesting bits */
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#define ISAC_RBCH_XAC 0x80
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#define ISAC_RBCH_VN1 0x40
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#define ISAC_RBCH_VN0 0x20
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#define ISAC_RBCH_OV 0x10
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/* the other 4 bits are the high bits of the receive byte count */
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#define ISAC_SPCR_SPU 0x80
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#define ISAC_SPCR_SAC 0x40
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#define ISAC_SPCR_SPM 0x20
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#define ISAC_SPCR_TLP 0x10
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#define ISAC_SPCR_C1C1 0x08
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#define ISAC_SPCR_C1C0 0x04
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#define ISAC_SPCR_C2C1 0x02
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#define ISAC_SPCR_C2C0 0x01
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#define ISAC_CIRR_SQC 0x80
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#define ISAC_CIRR_BAS 0x40
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/* bits 5-2 CODR */
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#define ISAC_CIRR_CIC0 0x02
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/* bit 0 is always 0 */
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/* C/I codes from bits 5-2 (>> 2 & 0xf) */
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/* the indications */
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#define ISAC_CIRR_IPU 0x07
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#define ISAC_CIRR_IDR 0x00
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#define ISAC_CIRR_ISD 0x02
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#define ISAC_CIRR_IDIS 0x03
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#define ISAC_CIRR_IEI 0x06
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#define ISAC_CIRR_IRSY 0x04
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#define ISAC_CIRR_IARD 0x08
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#define ISAC_CIRR_ITI 0x0a
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#define ISAC_CIRR_IATI 0x0b
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#define ISAC_CIRR_IAI8 0x0c
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#define ISAC_CIRR_IAI10 0x0d
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#define ISAC_CIRR_IDID 0x0f
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#define ISAC_CI_MASK 0x0f
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#define ISAC_CIXR_RSS 0x80
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#define ISAC_CIXR_BAC 0x40
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/* bits 5-2 CODX */
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#define ISAC_CIXR_TCX 0x02
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#define ISAC_CIXR_ECX 0x01
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/* in IOM-2 mode the low bits are always 1 */
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#define ISAC_CIX0_LOW 0x03
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/* C/I codes from bits 5-2 (>> 2 & 0xf) */
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/* the commands */
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#define ISAC_CIXR_CTIM 0
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#define ISAC_CIXR_CRS 0x01
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#define ISAC_CIXR_CSCZ 0x04
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#define ISAC_CIXR_CSSZ 0x02
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#define ISAC_CIXR_CAR8 0x08
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#define ISAC_CIXR_CAR10 0x09
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#define ISAC_CIXR_CARL 0x0a
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#define ISAC_CIXR_CDIU 0x0f
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#define ISAC_STCR_TSF 0x80
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#define ISAC_STCR_TBA2 0x40
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#define ISAC_STCR_TBA1 0x20
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#define ISAC_STCR_TBA0 0x10
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#define ISAC_STCR_ST1 0x08
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#define ISAC_STCR_ST0 0x04
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#define ISAC_STCR_SC1 0x02
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#define ISAC_STCR_SC0 0x01
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#define ISAC_ADF1_WTC1 0x80
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#define ISAC_ADF1_WTC2 0x40
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#define ISAC_ADF1_TEM 0x20
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#define ISAC_ADF1_PFS 0x10
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#define ISAC_ADF1_CFS 0x08
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#define ISAC_ADF1_FC2 0x04
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#define ISAC_ADF1_FC1 0x02
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#define ISAC_ADF1_ITF 0x01
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#define ISAC_ADF2_IMS 0x80
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/* all other bits are 0 */
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/* bits 7-5 are always 0 */
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#define ISAC_SQRR_SYN 0x10
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#define ISAC_SQRR_SQR1 0x08
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#define ISAC_SQRR_SQR2 0x04
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#define ISAC_SQRR_SQR3 0x02
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#define ISAC_SQRR_SQR4 0x01
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#define ISAC_SQXR_IDC 0x80
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#define ISAC_SQXR_CFS 0x40
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#define ISAC_SQXR_CI1E 0x20
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#define ISAC_SQXR_SQIE 0x10
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#define ISAC_SQXR_SQX1 0x08
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#define ISAC_SQXR_SQX2 0x04
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#define ISAC_SQXR_SQX3 0x02
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#define ISAC_SQXR_SQX4 0x01
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#endif /* I4B_ISAC_H_ */
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