387 lines
12 KiB
C
387 lines
12 KiB
C
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/* $NetBSD: if_liireg.h,v 1.1 2008/03/29 00:16:26 cube Exp $ */
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/*
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* Copyright (c) 2008 The NetBSD Foundation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI configuration space seems to be mapped in the first 0x100 bytes of
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* the register area.
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*/
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/* SPI Flash Control register */
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#define ATL2_SFC 0x0200
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#define SFC_STS_NON_RDY 0x00000001
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#define SFC_STS_WEN 0x00000002
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#define SFC_STS_WPEN 0x00000080
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#define SFC_DEV_STS_MASK 0x000000ff
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#define SFC_DEV_STS_SHIFT 0
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#define SFC_INS_MASK 0x07
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#define SFC_INS_SHIFT 8
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#define SFC_START 0x00000800
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#define SFC_EN_VPD 0x00002000
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#define SFC_LDSTART 0x00008000
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#define SFC_CS_HI_MASK 0x03
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#define SFC_CS_HI_SHIFT 16
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#define SFC_CS_HOLD_MASK 0x03
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#define SFC_CS_HOLD_SHIFT 18
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#define SFC_CLK_LO_MASK 0x03
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#define SFC_CLK_LO_SHIFT 20
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#define SFC_CLK_HI_MASK 0x03
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#define SFC_CLK_HI_SHIFT 22
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#define SFC_CS_SETUP_MASK 0x03
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#define SFC_CS_SETUP_SHIFT 24
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#define SFC_EROMPGSZ_MASK 0x03
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#define SFC_EROMPGSZ_SHIFT 26
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#define SFC_WAIT_READY 0x10000000
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/* SPI Flash Address register */
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#define ATL2_SF_ADDR 0x0204
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/* SPI Flash Data register */
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#define ATL2_SF_DATA 0x0208
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/* SPI Flash Configuration register */
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#define ATL2_SFCF 0x020c
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#define SFCF_LD_ADDR_MASK 0x00ffffff
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#define SFCF_LD_ADDR_SHIFT 0
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#define SFCF_VPD_ADDR_MASK 0x03
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#define SFCF_VPD_ADDR_SHIFT 24
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#define SFCF_LD_EXISTS 0x04000000
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/* SPI Flash op codes programmation registers */
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#define ATL2_SFOP_PROGRAM 0x0210
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#define ATL2_SFOP_SC_ERASE 0x0211
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#define ATL2_SFOP_CHIP_ERASE 0x0212
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#define ATL2_SFOP_RDID 0x0213
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#define ATL2_SFOP_WREN 0x0214
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#define ATL2_SFOP_RDSR 0x0215
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#define ATL2_SFOP_WRSR 0x0216
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#define ATL2_SFOP_READ 0x0217
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/* TWSI Control register, whatever that is */
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#define ATL2_TWSIC 0x0218
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#define TWSIC_LD_OFFSET_MASK 0x000000ff
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#define TWSIC_LD_OFFSET_SHIFT 0
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#define TWSIC_LD_SLV_ADDR_MASK 0x07
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#define TWSIC_LD_SLV_ADDR_SHIFT 8
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#define TWSIC_SW_LDSTART 0x00000800
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#define TWSIC_HW_LDSTART 0x00001000
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#define TWSIC_SMB_SLV_ADDR_MASK 0x7F
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#define TWSIC_SMB_SLV_ADDR_SHIFT 15
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#define TWSIC_LD_EXIST 0x00400000
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#define TWSIC_READ_FREQ_SEL_MASK 0x03
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#define TWSIC_READ_FREQ_SEL_SHIFT 23
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#define TWSIC_FREQ_SEL_100K 0
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#define TWSIC_FREQ_SEL_200K 1
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#define TWSIC_FREQ_SEL_300K 2
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#define TWSIC_FREQ_SEL_400K 3
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#define TWSIC_WRITE_FREQ_SEL_MASK 0x03
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#define TWSIC_WRITE_FREQ_SEL_SHIFT 24
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/* PCI-Express Device Misc. Control register? (size unknown) */
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#define ATL2_PCEDMC 0x021c
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#define PCEDMC_RETRY_BUFDIS 0x01
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#define PCEDMC_EXT_PIPE 0x02
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#define PCEDMC_SPIROM_EXISTS 0x04
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#define PCEDMC_SERDES_ENDIAN 0x08
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#define PCEDMC_SERDES_SEL_DIN 0x10
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/* PCI-Express PHY Miscellaneous register (size unknown) */
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#define ATL2_PCEPM 0x1000
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#define PCEPM_FORCE_RCV_DET 0x04
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/* PCI-Express DLL TX Control register */
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#define ATL2_PCEDTXC 0x1104
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#define PCEDTX_SEL_NOR_CLK 0x00000400
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#define PCEDTX_DEF 0x00000568
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/* PCI-Express-related register (LTSSM test mode) */
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#define ATL2_PCELTM 0x12fc
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#define PCELTM_DEF 0x00006500
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/* Selene Master Control register */
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#define ATL2_SMC 0x1400
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#define SMC_SOFT_RST 0x00000001
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#define SMC_MTIMER_EN 0x00000002
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#define SMC_ITIMER_EN 0x00000004
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#define SMC_MANUAL_INT 0x00000008
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#define SMC_REV_NUM_MASK 0xff
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#define SMC_REV_NUM_SHIFT 16
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#define SMC_DEV_ID_MASK 0xff
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#define SMC_DEV_ID_SHIFT 24
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/* Timer Initial Value register */
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#define ATL2_TIV 0x1404
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/* IRQ Moderator Timer Initial Value register */
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#define ATL2_IMTIV 0x1408
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/* PHY Control register */
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#define ATL2_PHYC 0x140c
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#define PHYC_ENABLE 0x0001
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/* IRQ Anti-Lost Timer Initial Value register
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--> Time allowed for software to clear the interrupt */
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#define ATL2_IALTIV 0x140e
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/* Block Idle Status register
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--> Bit set if matching state machine is not idle */
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#define ATL2_BIS 0x1410
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#define BIS_RXMAC 0x00000001
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#define BIS_TXMAC 0x00000002
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#define BIS_DMAR 0x00000004
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#define BIS_DMAW 0x00000008
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/* MDIO Control register */
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#define ATL2_MDIOC 0x1414
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#define MDIOC_DATA_MASK 0x0000ffff
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#define MDIOC_DATA_SHIFT 0
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#define MDIOC_REG_MASK 0x1f
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#define MDIOC_REG_SHIFT 16
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#define MDIOC_WRITE 0x00000000
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#define MDIOC_READ 0x00200000
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#define MDIOC_SUP_PREAMBLE 0x00400000
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#define MDIOC_START 0x00800000
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#define MDIOC_CLK_SEL_MASK 0x07
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#define MDIOC_CLK_SEL_SHIFT 24
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#define MDIOC_CLK_25_4 0
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#define MDIOC_CLK_25_6 2
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#define MDIOC_CLK_25_8 3
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#define MDIOC_CLK_25_10 4
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#define MDIOC_CLK_25_14 5
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#define MDIOC_CLK_25_20 6
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#define MDIOC_CLK_25_28 7
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#define MDIOC_BUSY 0x08000000
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/* Time to wait for MDIO, waiting for 2us in-between */
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#define MDIO_WAIT_TIMES 10
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/* SerDes Lock Detect Control and Status register */
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#define ATL2_SERDES 0x1424
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#define SERDES_LOCK_DETECT 0x01
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#define SERDES_LOCK_DETECT_EN 0x02
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/* MAC Control register */
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#define ATL2_MACC 0x1480
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#define MACC_TX_EN 0x00000001
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#define MACC_RX_EN 0x00000002
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#define MACC_TX_FLOW_EN 0x00000004
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#define MACC_RX_FLOW_EN 0x00000008
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#define MACC_LOOPBACK 0x00000010
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#define MACC_FDX 0x00000020
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#define MACC_ADD_CRC 0x00000040
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#define MACC_PAD 0x00000080
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#define MACC_PREAMBLE_LEN_MASK 0x0f
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#define MACC_PREAMBLE_LEN_SHIFT 10
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#define MACC_STRIP_VLAN 0x00004000
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#define MACC_PROMISC_EN 0x00008000
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#define MACC_DBG_TX_BKPRESSURE 0x00100000
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#define MACC_ALLMULTI_EN 0x02000000
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#define MACC_BCAST_EN 0x04000000
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#define MACC_MACLP_CLK_PHY 0x08000000
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#define MACC_HDX_LEFT_BUF_MASK 0x0f
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#define MACC_HDX_LEFT_BUF_SHIFT 28
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/* MAC IPG/IFG Control register */
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#define ATL2_MIPFG 0x1484
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#define MIPFG_IPGT_MASK 0x0000007f
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#define MIPFG_IPGT_SHIFT 0
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#define MIPFG_MIFG_MASK 0xff
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#define MIPFG_MIFG_SHIFT 8
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#define MIPFG_IPGR1_MASK 0x7f
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#define MIPFG_IPGR1_SHIFT 16
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#define MIPFG_IPGR2_MASK 0x7f
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#define MIPFG_IPGR2_SHIFT 24
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/* MAC Address registers */
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#define ATL2_MAC_ADDR_0 0x1488
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#define ATL2_MAC_ADDR_1 0x148c
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/* Multicast Hash Table register */
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#define ATL2_MHT 0x1490
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/* MAC Half-Duplex Control register */
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#define ATL2_MHDC 0x1498
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#define MHDC_LCOL_MASK 0x000003ff
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#define MHDC_LCOL_SHIFT 0
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#define MHDC_RETRY_MASK 0x0f
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#define MHDC_RETRY_SHIFT 12
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#define MHDC_EXC_DEF_EN 0x00010000
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#define MHDC_NO_BACK_C 0x00020000
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#define MHDC_NO_BACK_P 0x00040000
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#define MHDC_ABEDE 0x00080000
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#define MHDC_ABEBT_MASK 0x0f
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#define MHDC_ABEBT_SHIFT 20
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#define MHDC_JAMIPG_MASK 0x0f
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#define MHDC_JAMIPG_SHIFT 24
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/* MTU Control register */
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#define ATL2_MTU 0x149c
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/* WOL Control register */
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#define ATL2_WOLC
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#define WOLC_PATTERN_EN 0x00000001
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#define WOLC_PATTERN_PME_EN 0x00000002
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#define WOLC_MAGIC_EN 0x00000004
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#define WOLC_MAGIC_PME_EN 0x00000008
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#define WOLC_LINK_CHG_EN 0x00000010
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#define WOLC_LINK_CHG_PME_EN 0x00000020
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#define WOLC_PATTERN_ST 0x00000100
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#define WOLC_MAGIC_ST 0x00000200
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#define WOLC_LINK_CHG_ST 0x00000400
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#define WOLC_PT0_EN 0x00010000
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#define WOLC_PT1_EN 0x00020000
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#define WOLC_PT2_EN 0x00040000
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#define WOLC_PT3_EN 0x00080000
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#define WOLC_PT4_EN 0x00100000
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#define WOLC_PT0_MATCH 0x01000000
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#define WOLC_PT1_MATCH 0x02000000
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#define WOLC_PT2_MATCH 0x04000000
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#define WOLC_PT3_MATCH 0x08000000
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#define WOLC_PT4_MATCH 0x10000000
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/* Internal SRAM Partition register */
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#define ATL2_SRAM_TXRAM_END 0x1500
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#define ATL2_SRAM_RXRAM_END 0x1502
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/* Descriptor Control registers */
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#define ATL2_DESC_BASE_ADDR_HI 0x1540
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#define ATL2_TXD_BASE_ADDR_LO 0x1544
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#define ATL2_TXD_BUFFER_SIZE 0x1548
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#define ATL2_TXS_BASE_ADDR_LO 0x154c
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#define ATL2_TXS_NUM_ENTRIES 0x1550
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#define ATL2_RXD_BASE_ADDR_LO 0x1554
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#define ATL2_RXD_NUM_ENTRIES 0x1558
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/* DMAR Control register */
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#define ATL2_DMAR 0x1580
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#define DMAR_EN 0x01
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/* TX Cur-Through Control register */
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#define ATL2_TX_CUT_THRESH 0x1590
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/* DMAW Control register */
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#define ATL2_DMAW 0x15a0
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#define DMAW_EN 0x01
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/* Flow Control registers */
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#define ATL2_PAUSE_ON_TH 0x15a8
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#define ATL2_PAUSE_OFF_TH 0x15aa
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/* Mailbox registers */
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#define ATL2_MB_TXD_WR_IDX 0x15f0
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#define ATL2_MB_RXD_RD_IDX 0x15f4
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/* Interrupt Status register */
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#define ATL2_ISR 0x1600
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#define ISR_TIMER 0x00000001
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#define ISR_MANUAL 0x00000002
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#define ISR_RXF_OV 0x00000004
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#define ISR_TXF_UR 0x00000008
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#define ISR_TXS_OV 0x00000010
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#define ISR_RXS_OV 0x00000020
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#define ISR_LINK_CHG 0x00000040
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#define ISR_HOST_TXD_UR 0x00000080
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#define ISR_HOST_RXD_OV 0x00000100
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#define ISR_DMAR_TO_RST 0x00000200
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#define ISR_DMAW_TO_RST 0x00000400
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#define ISR_PHY 0x00000800
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#define ISR_TS_UPDATE 0x00010000
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#define ISR_RS_UPDATE 0x00020000
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#define ISR_TX_EARLY 0x00040000
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#define ISR_UR_DETECTED 0x01000000
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#define ISR_FERR_DETECTED 0x02000000
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#define ISR_NFERR_DETECTED 0x04000000
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#define ISR_CERR_DETECTED 0x08000000
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#define ISR_PHY_LINKDOWN 0x10000000
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#define ISR_DIS_INT 0x80000000
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#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | \
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ISR_HOST_TXD_UR | ISR_TS_UPDATE | \
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ISR_TX_EARLY)
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#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | \
|
||
|
|
ISR_HOST_RXD_OV | ISR_RS_UPDATE)
|
||
|
|
|
||
|
|
/* Interrupt Mask register */
|
||
|
|
#define ATL2_IMR 0x1604
|
||
|
|
#define IMR_NORMAL_MASK (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST | \
|
||
|
|
ISR_PHY | ISR_PHY_LINKDOWN | \
|
||
|
|
ISR_TS_UPDATE | ISR_RS_UPDATE | \
|
||
|
|
ISR_MANUAL)
|
||
|
|
|
||
|
|
/* MAC RX Statistics registers */
|
||
|
|
#define ATL2_STS_RX_PAUSE 0x1700
|
||
|
|
#define ATL2_STS_RXD_OV 0x1704
|
||
|
|
#define ATL2_STS_RXS_OV 0x1708
|
||
|
|
#define ATL2_STS_RX_FILTER 0x170c
|
||
|
|
|
||
|
|
struct tx_pkt_header {
|
||
|
|
uint16_t txph_size;
|
||
|
|
#define ATL2_TXH_ADD_VLAN_TAG 0x8000
|
||
|
|
uint16_t txph_vlan;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
struct tx_pkt_status {
|
||
|
|
uint16_t txps_size;
|
||
|
|
uint16_t txps_flags :15;
|
||
|
|
#define ATL2_TXF_SUCCESS 0x0001
|
||
|
|
#define ATL2_TXF_BCAST 0x0002
|
||
|
|
#define ATL2_TXF_MCAST 0x0004
|
||
|
|
#define ATL2_TXF_PAUSE 0x0008
|
||
|
|
#define ATL2_TXF_CTRL 0x0010
|
||
|
|
#define ATL2_TXF_DEFER 0x0020
|
||
|
|
#define ATL2_TXF_EXC_DEFER 0x0040
|
||
|
|
#define ATL2_TXF_SINGLE_COL 0x0080
|
||
|
|
#define ATL2_TXF_MULTI_COL 0x0100
|
||
|
|
#define ATL2_TXF_LATE_COL 0x0200
|
||
|
|
#define ATL2_TXF_ABORT_COL 0x0400
|
||
|
|
#define ATL2_TXF_UNDERRUN 0x0800
|
||
|
|
uint16_t txps_update:1;
|
||
|
|
} __packed;
|
||
|
|
|
||
|
|
struct rx_pkt {
|
||
|
|
uint16_t rxp_size;
|
||
|
|
uint16_t rxp_flags :15;
|
||
|
|
#define ATL2_RXF_SUCCESS 0x0001
|
||
|
|
#define ATL2_RXF_BCAST 0x0002
|
||
|
|
#define ATL2_RXF_MCAST 0x0004
|
||
|
|
#define ATL2_RXF_PAUSE 0x0008
|
||
|
|
#define ATL2_RXF_CTRL 0x0010
|
||
|
|
#define ATL2_RXF_CRC 0x0020
|
||
|
|
#define ATL2_RXF_CODE 0x0040
|
||
|
|
#define ATL2_RXF_RUNT 0x0080
|
||
|
|
#define ATL2_RXF_FRAG 0x0100
|
||
|
|
#define ATL2_RXF_TRUNC 0x0200
|
||
|
|
#define ATL2_RXF_ALIGN 0x0400
|
||
|
|
#define ATL2_RXF_VLAN 0x0800
|
||
|
|
uint16_t rxp_update:1;
|
||
|
|
uint16_t rxp_vlan;
|
||
|
|
uint16_t __pad;
|
||
|
|
uint8_t rxp_data[1528];
|
||
|
|
} __packed;
|