78 lines
2.3 KiB
Plaintext
78 lines
2.3 KiB
Plaintext
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* MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP
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* M68000 Hi-Performance Microprocessor Division
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* M68040 Software Package
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*
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* M68040 Software Package Copyright (c) 1993, 1994 Motorola Inc.
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* All rights reserved.
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*
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* THE SOFTWARE is provided on an "AS IS" basis and without warranty.
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* To the maximum extent permitted by applicable law,
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* MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
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* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
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* PARTICULAR PURPOSE and any warranty against infringement with
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* regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
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* and any accompanying written materials.
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*
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* To the maximum extent permitted by applicable law,
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* IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
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* (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS
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* PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
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* OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
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* SOFTWARE. Motorola assumes no responsibility for the maintenance
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* and support of the SOFTWARE.
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*
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* You are hereby granted a copyright license to use, modify, and
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* distribute the SOFTWARE so long as this entire notice is retained
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* without alteration in any modified and/or redistributed versions,
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* and that such modified versions are clearly identified as such.
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* No licenses are granted by implication, estoppel or otherwise
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* under any patents or trademarks of Motorola, Inc.
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*
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* FPSP.sa 3.1 12/10/90
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*
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* Init file for testing FPSP software package.
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*
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* Takes over the exception vectors that the FPSP handles.
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*
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FPSP IDNT 2,1 Motorola 040 Floating Point Software Package
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CODE_ST equ $10000 ;address of test code start
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FLINE_VEC equ $2c
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BSUN_VEC equ $c0
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INEX2_VEC equ $c4
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DZ_VEC equ $c8
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UNFL_VEC equ $cc
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OPERR_VEC equ $d0
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OVFL_VEC equ $d4
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SNAN_VEC equ $d8
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UNSUP_VEC equ $dc
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xref fline,unsupp
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xref bsun,inex,dz,unfl
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xref operr,ovfl,snan
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section 7
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* Load vector table with addresses of FPSP routines and
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* branch to CODE_ST, start address of test code.
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xdef start
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start:
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movec.l VBR,a0
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move.l #fline,FLINE_VEC(a0)
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move.l #bsun,BSUN_VEC(a0)
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move.l #inex,INEX2_VEC(a0)
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move.l #dz,DZ_VEC(a0)
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move.l #unfl,UNFL_VEC(a0)
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move.l #operr,OPERR_VEC(a0)
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move.l #ovfl,OVFL_VEC(a0)
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move.l #snan,SNAN_VEC(a0)
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move.l #unsupp,UNSUP_VEC(a0)
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jmp CODE_ST
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end
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