1995-04-23 02:18:17 +04:00
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/* $NetBSD: fdreg.h,v 1.2 1995/04/22 22:18:21 leo Exp $ */
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1995-03-26 11:12:03 +04:00
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/*
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* Copyright (c) 1995 Leo Weppelman.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Leo Weppelman.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FDREG_H
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#define _FDREG_H
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/*
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* Atari TT hardware:
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* Western Digital 1772 Floppy Disk Controller.
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*/
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/*
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* Accessing the FDC registers is indirect through ST-specific
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* DMA circuitry. See also dma.h.
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*/
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1995-04-23 02:18:17 +04:00
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#define FDC_CS (DMA_FDC ) /* command/status */
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#define FDC_TR (DMA_FDC| DMA_A0) /* track register */
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#define FDC_SR (DMA_FDC|DMA_A1 ) /* sector register */
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#define FDC_DR (DMA_FDC|DMA_A1|DMA_A0) /* data register */
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1995-03-26 11:12:03 +04:00
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/*
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* commands (relevant bits/fields indicated)
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*/
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#define RESTORE 0x00 /* ( HVRR) seek to track 0 */
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#define SEEK 0x10 /* ( HVRR) seek to track */
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#define STEP 0x20 /* (UHVRR) step in same direction */
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#define STEPI 0x40 /* (UHVRR) step in */
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#define STEPO 0x60 /* (UHVRR) step out */
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#define F_READ 0x80 /* (MHE00) read sector */
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#define F_WRITE 0xA0 /* (MHEPA) write sector */
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#define READID 0xC0 /* ( HE00) read sector ID */
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#define READTR 0xE0 /* ( HE00) read track */
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#define WRITETR 0xF0 /* ( HEP0) write track */
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#define IRUPT 0xD0 /* ( IIII) force interrupt */
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/*
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* other bits/fields in command register
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*/
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#define RATE6 0x00 /* not 2, but 6 msec steprate */
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#define RATE12 0x01 /* not 3, but 12 msec steprate */
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#define RATE2 0x02 /* not 5, but 2 msec steprate */
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#define RATE3 0x03 /* not 6, but 3 msec steprate */
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#define VBIT 0x04 /* verify sector ID */
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#define HBIT 0x08 /* suppress motor on sequence */
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#define UBIT 0x10 /* update track register */
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#define EBIT 0x04 /* wait 30 msec to settle */
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#define MBIT 0x10 /* multi-sector */
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#define PBIT 0x02 /* write precompensate */
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#define A0BIT 0x01 /* suppress (?) data address mark */
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#define IINDEX 0x04 /* interrupt on each index pulse */
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#define IFORCE 0x08 /* force interrupt */
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/*
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* status register
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*/
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#define BUSY 0x01 /* set if command under execution */
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#define DRQ 0x02 /* Data Register status (pin c1) */
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#define LD_T00 0x04 /* lost data; track 00 */
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#define CRCERR 0x08 /* CRC error */
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#define RNF 0x10 /* Record Not Found */
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#define RT_SU 0x20 /* Record Type; Spin Up completed */
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#define WRI_PRO 0x40 /* Write Protected */
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#define MOTORON 0x80 /* Motor On */
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#endif /* _FDREG_H */
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