1999-09-16 09:58:18 +04:00
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/* $NetBSD: iophyreg.h,v 1.2 1999/09/16 05:58:18 soren Exp $ */
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1999-09-05 04:40:27 +04:00
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/*
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* Copyright (c) 1998, 1999 Soren S. Jorvang.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_IOPHYREG_H_
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#define _DEV_MII_IOPHYREG_H_
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/*
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* Intel 82553 PHY registers
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*/
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#define MII_IOPHY_EXT0 0x10 /* Extended Register 0 */
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#define EXT0_JABDIS 0x8000 /* jabber disabled */
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#define EXT0_LINKDIS 0x4000 /* link integrity disable */
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#define EXT0_TEST4 0x2000
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#define EXT0_TEST3 0x1000
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#define EXT0_TEST2 0x0800
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#define EXT0_TEST1 0x0400
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#define EXT0_TEST0 0x0200
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#define EXT0_FORCE100 0x0100 /* force 100 Mbps operation */
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#define EXT0_REVMASK 0x00e0 /* 82553 chip revision */
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#define EXT0_HSQ 0x0010
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#define EXT0_LSQ 0x0008
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#define EXT0_WAKEUP 0x0004 /* disable auto power-down */
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#define EXT0_SPEED 0x0002 /* current speed 10/100 */
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#define EXT0_DUPLEX 0x0001 /* current duplex setting */
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#define MII_IOPHY_EXT1 0x14 /* Extended Register 1 */
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#define EXT1_PAIR_SKEW_ERR 0x8000 /* pair skew error */
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#define EXT1_DC_BALANCE_ERR 0x4000 /* DC balance error */
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#define EXT1_INVALID_CODE_ERR 0x2000 /* invalid code error */
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#define EXT1_BAD_CODE_ERR 0x1000 /* bad code error */
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#define EXT1_EOP_ERR 0x0800 /* EOP error */
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#define EXT1_MANCHESTER_ERR 0x0400 /* Manchester code error */
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#define EXT1_CH2_EOF_ERR 0x0200 /* channel 2 EOF detection error */
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#define EXT1_DTE_MODE_SEL 0x0100 /* external DTE mode */
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#define EXT1_LINE_RPTR_MODE_SEL 0x0080 /* line repeater mode */
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#define EXT1_EXT_TEST_MODE_SEL 0x0040 /* external test mode */
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#define EXT1_MII_RPTR_MODE_SEL 0x0020 /* MII repeater mode */
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#define EXT1_CH2_POLARITY_ERR 0x0010 /* channel 2 polarity error */
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#define EXT1_CH3_POLARITY_ERR 0x0008 /* channel 3 polarity error */
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#define EXT1_CH4_POLARITY_ERR 0x0004 /* channel 4 polarity error */
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#define EXT1_CH2_SFD_DETECT_ERR 0x0002 /* channel 2 SFD not found */
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#define MII_IOPHY_EXT2 0x15 /* Extended Register 2 (C step only) */
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#define EXT2_AUTONEG_SEL 0x8000 /* autonegotiation selected */
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#define EXT2_CH3_SFD_ERR 0x4000 /* channel 3 SFD not found */
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#define EXT2_CH4_SFD_ERR 0x2000 /* channel 4 SFD not found */
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#endif /* _DEV_MII_IOPHYREG_H_ */
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