2024-02-08 22:44:08 +03:00
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/* $NetBSD: amhphy.c,v 1.27 2024/02/08 19:44:08 andvar Exp $ */
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2001-08-25 08:06:26 +04:00
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for the 10BASE-T portion of the AMD Am79c901 PHY.
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*/
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2001-11-13 10:38:28 +03:00
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#include <sys/cdefs.h>
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2024-02-08 22:44:08 +03:00
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__KERNEL_RCSID(0, "$NetBSD: amhphy.c,v 1.27 2024/02/08 19:44:08 andvar Exp $");
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2001-11-13 10:38:28 +03:00
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2001-08-25 08:06:26 +04:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/amhphyreg.h>
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2008-05-04 21:06:09 +04:00
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static int amhphymatch(device_t, cfdata_t, void *);
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static void amhphyattach(device_t, device_t, void *);
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2001-08-25 08:06:26 +04:00
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2008-05-04 21:06:09 +04:00
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CFATTACH_DECL_NEW(amhphy, sizeof(struct mii_softc),
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2002-10-02 20:33:28 +04:00
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amhphymatch, amhphyattach, mii_phy_detach, mii_phy_activate);
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2001-08-25 08:06:26 +04:00
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2004-08-23 10:16:06 +04:00
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static int amhphy_service(struct mii_softc *, struct mii_data *, int);
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static void amhphy_status(struct mii_softc *);
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2001-08-25 08:06:26 +04:00
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2004-08-23 10:16:06 +04:00
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static const struct mii_phy_funcs amhphy_funcs = {
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2001-08-25 08:06:26 +04:00
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amhphy_service, amhphy_status, mii_phy_reset,
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};
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2004-08-23 10:16:06 +04:00
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static const struct mii_phydesc amhphys[] = {
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(yyAMD, 79c901),
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MII_PHY_END,
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2001-08-25 08:06:26 +04:00
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};
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2004-08-23 10:16:06 +04:00
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static int
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2008-05-04 21:06:09 +04:00
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amhphymatch(device_t parent, cfdata_t match, void *aux)
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2001-08-25 08:06:26 +04:00
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, amhphys) != NULL)
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2019-03-25 10:34:13 +03:00
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return 10;
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2001-08-25 08:06:26 +04:00
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2019-03-25 10:34:13 +03:00
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return 0;
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2001-08-25 08:06:26 +04:00
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}
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2004-08-23 10:16:06 +04:00
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static void
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2008-05-04 21:06:09 +04:00
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amhphyattach(device_t parent, device_t self, void *aux)
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2001-08-25 08:06:26 +04:00
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{
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2006-03-29 10:51:47 +04:00
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struct mii_softc *sc = device_private(self);
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2001-08-25 08:06:26 +04:00
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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mpd = mii_phy_match(ma, amhphys);
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2003-04-29 05:49:33 +04:00
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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2001-08-25 08:06:26 +04:00
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2008-05-04 21:06:09 +04:00
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sc->mii_dev = self;
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2001-08-25 08:06:26 +04:00
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_funcs = &amhphy_funcs;
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sc->mii_pdata = mii;
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2002-03-25 23:51:24 +03:00
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sc->mii_flags = ma->mii_flags;
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2001-08-25 08:06:26 +04:00
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2020-03-16 02:04:50 +03:00
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mii_lock(mii);
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2001-08-25 08:06:26 +04:00
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PHY_RESET(sc);
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Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
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PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
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sc->mii_capabilities &= ma->mii_capmask;
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2019-11-27 13:19:20 +03:00
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2020-03-16 02:04:50 +03:00
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mii_unlock(mii);
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2019-11-27 13:19:20 +03:00
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mii_phy_add_media(sc);
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2001-08-25 08:06:26 +04:00
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}
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2004-08-23 10:16:06 +04:00
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static int
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2001-08-25 22:04:01 +04:00
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amhphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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2001-08-25 08:06:26 +04:00
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
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uint16_t reg;
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2001-08-25 08:06:26 +04:00
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2020-03-16 02:04:50 +03:00
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KASSERT(mii_locked(mii));
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2001-08-25 08:06:26 +04:00
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switch (cmd) {
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case MII_POLLSTAT:
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2019-03-25 10:34:13 +03:00
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/* If we're not polling our PHY instance, just return. */
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2001-08-25 08:06:26 +04:00
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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2019-03-25 10:34:13 +03:00
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return 0;
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2001-08-25 08:06:26 +04:00
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
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PHY_READ(sc, MII_BMCR, ®);
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2001-08-25 08:06:26 +04:00
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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2019-03-25 10:34:13 +03:00
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return 0;
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2001-08-25 08:06:26 +04:00
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}
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2019-03-25 10:34:13 +03:00
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/* If the interface is not up, don't do anything. */
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2001-08-25 08:06:26 +04:00
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
|
2019-03-25 10:34:13 +03:00
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/* If we're not currently selected, just return. */
|
2001-08-25 08:06:26 +04:00
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
2019-03-25 10:34:13 +03:00
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return 0;
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2001-08-25 08:06:26 +04:00
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if (mii_phy_tick(sc) == EJUSTRETURN)
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2019-03-25 10:34:13 +03:00
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return 0;
|
2001-08-25 08:06:26 +04:00
|
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break;
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case MII_DOWN:
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mii_phy_down(sc);
|
2019-03-25 10:34:13 +03:00
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return 0;
|
2001-08-25 08:06:26 +04:00
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}
|
|
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/* Update the media status. */
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mii_phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
|
2019-03-25 10:34:13 +03:00
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return 0;
|
2001-08-25 08:06:26 +04:00
|
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|
}
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|
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|
2004-08-23 10:16:06 +04:00
|
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static void
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2001-08-25 22:04:01 +04:00
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amhphy_status(struct mii_softc *sc)
|
2001-08-25 08:06:26 +04:00
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{
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struct mii_data *mii = sc->mii_pdata;
|
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmsr, bmcr, ssr;
|
2001-08-25 08:06:26 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2001-08-25 08:06:26 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
PHY_READ(sc, MII_AMHPHY_SSR, &ssr);
|
2001-08-25 08:06:26 +04:00
|
|
|
|
|
|
|
if (ssr & SSR_LS)
|
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2001-08-25 08:06:26 +04:00
|
|
|
if (bmcr & BMCR_ISO) {
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
|
|
|
if (bmcr & BMCR_AUTOEN) {
|
|
|
|
/*
|
2019-11-26 11:21:03 +03:00
|
|
|
* The media status bits are only valid if autonegotiation
|
2001-08-25 08:06:26 +04:00
|
|
|
* has completed (or it's disabled).
|
|
|
|
*/
|
|
|
|
if ((bmsr & BMSR_ACOMP) == 0) {
|
|
|
|
/* Erg, still trying, I guess... */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ssr & SSR_S) {
|
|
|
|
/*
|
2024-02-08 22:44:08 +03:00
|
|
|
* This shouldn't really ever happen, since it's
|
2019-03-25 10:34:13 +03:00
|
|
|
* a 10BASE-T only PHY. But the bit exists, according
|
|
|
|
* to the documentation, so we pay attention to it.
|
2001-08-25 08:06:26 +04:00
|
|
|
*/
|
|
|
|
mii->mii_media_active |= IFM_100_TX;
|
|
|
|
} else
|
|
|
|
mii->mii_media_active |= IFM_10_T;
|
|
|
|
if (ssr & SSR_FD)
|
|
|
|
mii->mii_media_active |= IFM_FDX;
|
2014-06-16 20:48:16 +04:00
|
|
|
else
|
|
|
|
mii->mii_media_active |= IFM_HDX;
|
2001-08-25 08:06:26 +04:00
|
|
|
} else
|
|
|
|
mii->mii_media_active = ife->ifm_media;
|
|
|
|
}
|