112 lines
3.8 KiB
C
112 lines
3.8 KiB
C
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/*
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* Copyright (c) 1993 Philip A. Nelson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Philip A. Nelson.
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* 4. The name of Philip A. Nelson may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY PHILIP NELSON ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL PHILIP NELSON BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* dp.h: defines for the dp driver.
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*
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* $Id: dpreg.h,v 1.1.1.1 1993/09/09 23:53:53 phil Exp $
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*/
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/* Most of this comes from the Minix dp driver by Bruce Culbertson. */
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/* NCR 8490 SCSI controller registers
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*/
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#define DP_CTL 0xffd00000 /* base for control registers */
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#define DP_DMA 0xffe00000 /* base for data registers */
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#define DP_DMA_EOP (DP_DMA | A22) /* SCSI DMA with EOP asserted */
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#define A22 (1 << 22)
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#define DP_CURDATA (DP_CTL+0)
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#define DP_OUTDATA (DP_CTL+0)
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#define DP_ICMD (DP_CTL+1)
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#define DP_MODE (DP_CTL+2)
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#define DP_TCMD (DP_CTL+3)
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#define DP_STAT1 (DP_CTL+4)
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#define DP_STAT2 (DP_CTL+5)
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#define DP_START_SEND (DP_CTL+5)
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#define DP_INDATA (DP_CTL+6)
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#define DP_EMR_ISR (DP_CTL+7)
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/* Bits in NCR 8490 registers
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*/
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#define DP_A_RST 0x80
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#define DP_A_SEL 0x04
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#define DP_S_SEL 0x02
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#define DP_S_REQ 0x20
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#define DP_S_BSY 0x40
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#define DP_S_BSYERR 0x04
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#define DP_S_PHASE 0x08
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#define DP_S_IRQ 0x10
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#define DP_S_DRQ 0x40
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#define DP_M_DMA 0x02
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#define DP_M_BSY 0x04
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#define DP_ENABLE_DB 0x01
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#define DP_EMODE 0x40 /* enhanced mode */
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#define DP_EF_NOP 0x00 /* enhanced functions */
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#define DP_EF_RESETIP 0x02
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#define DP_EF_START_RCV 0x04
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#define DP_EF_ISR_NEXT 0x06
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#define DP_EMR_APHS 0x80
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#define DP_ISR_BSYERR 0x04
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#define DP_ISR_APHS 0x08
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#define DP_ISR_DPHS 0x10
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#define DP_INT_MASK (~(DP_ISR_APHS | DP_ISR_BSYERR))
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#define dp_clear_isr() /* clear 8490 interrupts */ \
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RD_ADR (u_char, DP_EMR_ISR); \
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WR_ADR (u_char, DP_EMR_ISR, DP_EF_RESETIP); \
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WR_ADR (u_char, DP_EMR_ISR, DP_EF_NOP | DP_EMR_APHS);
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/* Status of interrupt routine.
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*/
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#define ISR_NOTDONE 0
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#define ISR_OK 1
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#define ISR_BSYERR 2
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#define ISR_RSTERR 3
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#define ISR_BADPHASE 4
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#define ISR_TIMEOUT 5
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#define ISR_DMACNTERR 6
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#define ICU_ADR 0xfffffe00
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#define ICU_IO (ICU_ADR+20)
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#define ICU_DIR (ICU_ADR+21)
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#define ICU_DATA (ICU_ADR+19)
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#define ICU_SCSI_BIT 0x80
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/* This tells when to poll and when to sleep while waiting for next
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* SCSI phase. Sleep after command phase and out data phase.
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*/
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#define SCSI_SLEEP ((1<<PH_CMD) | (1<<PH_ODATA))
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/* Miscellaneous
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*/
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#define MAX_WAIT 2000000
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#define OK 1
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#define NOT_OK 0
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