2010-11-13 09:44:11 +03:00
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMXGPIOREG_H
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#define _ARM_IMX_IMXGPIOREG_H
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#define GPIO_SIZE 0x0020 /* Size of GPIO registers */
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#define GPIO_DR 0x0000 /* GPIO Data (RW) */
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#define GPIO_DIR 0x0004 /* GPIO Direction (RW), 1=Output */
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#define GPIO_PSR 0x0008 /* GPIO Pad Status (R) */
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#define GPIO_ICR1 0x000c /* GPIO Interrupt Configuration 1 (RW) */
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#define GPIO_ICR2 0x0010 /* GPIO Interrupt Configuration 2 (RW) */
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#define GPIO_IMR 0x0014 /* GPIO Interrupt Mask (RW) */
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#define GPIO_ISR 0x0018 /* GPIO Interrupt Status (RW, W1C) */
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#define GPIO_EDGE_SEL 0x001c /* GPIO Edge Select Register (i.MX51 only) */
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#define GPIO_ICR_LEVEL_LOW 0
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#define GPIO_ICR_LEVEL_HIGH 1
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#define GPIO_ICR_EDGE_RISING 2
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#define GPIO_ICR_EDGE_FALLING 3
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2010-11-30 16:05:27 +03:00
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#define GPIO_NPINS 32
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2010-11-13 09:44:11 +03:00
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#endif /* _ARM_IMX_IMXGPIOREG_H */
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