2018-11-26 10:45:47 +03:00
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/* $NetBSD: tprof_x86.c,v 1.6 2018/11/26 07:45:47 knakahara Exp $ */
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2018-07-13 10:56:29 +03:00
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/*
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* Copyright (c) 2018 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Maxime Villard.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <err.h>
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#include <machine/specialreg.h>
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#include <dev/tprof/tprof_ioctl.h>
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#include "../tprof.h"
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int tprof_event_init(uint32_t);
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void tprof_event_list(void);
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void tprof_event_lookup(const char *, struct tprof_param *);
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struct name_to_event {
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const char *name;
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uint64_t event;
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uint64_t unit;
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bool enabled;
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};
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struct event_table {
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const char *tablename;
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struct name_to_event *names;
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size_t nevents;
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struct event_table *next;
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};
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static struct event_table *cpuevents = NULL;
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static void x86_cpuid(unsigned int *eax, unsigned int *ebx,
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unsigned int *ecx, unsigned int *edx)
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{
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asm volatile("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (*eax), "2" (*ecx));
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}
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/* -------------------------------------------------------------------------- */
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/*
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* Intel Architectural Version 1.
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*/
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static struct name_to_event intel_arch1_names[] = {
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/* Event Name - Event Select - UMask */
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{ "unhalted-core-cycles", 0x3C, 0x00, true },
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{ "instruction-retired", 0xC0, 0x00, true },
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{ "unhalted-reference-cycles", 0x3C, 0x01, true },
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{ "llc-reference", 0x2E, 0x4F, true },
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{ "llc-misses", 0x2E, 0x41, true },
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{ "branch-instruction-retired", 0xC4, 0x00, true },
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{ "branch-misses-retired", 0xC5, 0x00, true },
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};
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static struct event_table intel_arch1 = {
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.tablename = "Intel Architectural Version 1",
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.names = intel_arch1_names,
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.nevents = sizeof(intel_arch1_names) /
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sizeof(struct name_to_event),
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.next = NULL
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};
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static struct event_table *
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init_intel_arch1(void)
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{
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unsigned int eax, ebx, ecx, edx;
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struct event_table *table;
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size_t i;
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eax = 0x0A;
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ebx = 0;
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ecx = 0;
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edx = 0;
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x86_cpuid(&eax, &ebx, &ecx, &edx);
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table = &intel_arch1;
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for (i = 0; i < table->nevents; i++) {
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/* Disable the unsupported events. */
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if ((ebx & (i << 1)) != 0)
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table->names[i].enabled = false;
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}
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return table;
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}
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2018-11-15 10:20:31 +03:00
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/*
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* Intel Silvermont/Airmont.
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*/
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static struct name_to_event intel_silvermont_airmont_names[] = {
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{ "REHABQ.LD_BLOCK_ST_FORWARD", 0x03, 0x01, true },
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{ "REHABQ.LD_BLOCK_STD_NOTREADY", 0x03, 0x02, true },
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{ "REHABQ.ST_SPLITS", 0x03, 0x04, true },
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{ "REHABQ.LD_SPLITS", 0x03, 0x08, true },
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{ "REHABQ.LOCK", 0x03, 0x10, true },
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{ "REHABQ.STA_FULL", 0x03, 0x20, true },
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{ "REHABQ.ANY_LD", 0x03, 0x40, true },
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{ "REHABQ.ANY_ST", 0x03, 0x80, true },
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{ "MEM_UOPS_RETIRED.L1_MISS_LOADS", 0x04, 0x01, true },
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{ "MEM_UOPS_RETIRED.L2_HIT_LOADS", 0x04, 0x02, true },
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{ "MEM_UOPS_RETIRED.L2_MISS_LOADS", 0x04, 0x04, true },
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{ "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0x04, 0x08, true },
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{ "MEM_UOPS_RETIRED.UTLB_MISS", 0x04, 0x10, true },
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{ "MEM_UOPS_RETIRED.HITM", 0x04, 0x20, true },
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{ "MEM_UOPS_RETIRED.ALL_LOADS", 0x04, 0x40, true },
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{ "MEM_UOP_RETIRED.ALL_STORES", 0x04, 0x80, true },
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{ "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
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{ "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
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{ "PAGE_WALKS.WALKS", 0x05, 0x03, true },
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{ "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
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{ "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
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{ "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
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{ "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
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{ "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
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{ "CPU_CLK_UNHALTED.REF_P", 0x3C, 0x01, true },
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{ "ICACHE.HIT", 0x80, 0x01, true },
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{ "ICACHE.MISSES", 0x80, 0x02, true },
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{ "ICACHE.ACCESSES", 0x80, 0x03, true },
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{ "OFFCORE_RESPONSE_0", 0xB7, 0x01, true },
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{ "OFFCORE_RESPONSE_1", 0xB7, 0x02, true },
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{ "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
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{ "UOPS_RETIRED.MS", 0xC2, 0x01, true },
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{ "UOPS_RETIRED.ALL", 0xC2, 0x10, true },
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{ "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
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{ "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
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{ "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
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{ "MACHINE_CLEARS.ALL", 0xC3, 0x08, true },
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{ "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
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{ "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
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{ "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
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{ "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
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{ "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
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{ "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
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{ "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
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{ "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
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{ "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
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{ "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
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{ "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
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{ "BR_MISP_RETIRED.FAR", 0xC5, 0xBF, true },
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{ "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
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{ "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
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{ "BR_MISP_RETIRED.CALL", 0xC5, 0xF9, true },
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{ "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
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{ "BR_MISP_RETIRED.REL_CALL", 0xC5, 0xFD, true },
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{ "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
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{ "NO_ALLOC_CYCLES.ROB_FULL", 0xCA, 0x01, true },
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{ "NO_ALLOC_CYCLES.RAT_STALL", 0xCA, 0x20, true },
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{ "NO_ALLOC_CYCLES.ALL", 0xCA, 0x3F, true },
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{ "NO_ALLOC_CYCLES.NOT_DELIVERED", 0xCA, 0x50, true },
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{ "RS_FULL_STALL.MEC", 0xCB, 0x01, true },
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{ "RS_FULL_STALL.ALL", 0xCB, 0x1F, true },
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{ "CYCLES_DIV_BUSY.ANY", 0xCD, 0x01, true },
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{ "BACLEARS.ALL", 0xE6, 0x01, true },
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{ "BACLEARS.RETURN", 0xE6, 0x08, true },
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{ "BACLEARS.COND", 0xE6, 0x10, true },
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{ "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
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};
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static struct event_table intel_silvermont_airmont = {
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.tablename = "Intel Silvermont/Airmont",
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.names = intel_silvermont_airmont_names,
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.nevents = sizeof(intel_silvermont_airmont_names) /
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sizeof(struct name_to_event),
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.next = NULL
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};
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static struct event_table *
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init_intel_silvermont_airmont(void)
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{
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return &intel_silvermont_airmont;
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}
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2018-11-26 10:45:47 +03:00
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/*
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* Intel Goldmont
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*/
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static struct name_to_event intel_goldmont_names[] = {
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{ "LD_BLOCKS.ALL_BLOCK", 0x03, 0x10, true },
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{ "LD_BLOCKS.UTLB_MISS", 0x03, 0x08, true },
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{ "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
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{ "LD_BLOCKS.DATA_UNKNOWN", 0x03, 0x01, true },
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{ "LD_BLOCKS.4K_ALIAS", 0x03, 0x04, true },
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{ "PAGE_WALKS.D_SIDE_CYCLES", 0x05, 0x01, true },
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{ "PAGE_WALKS.I_SIDE_CYCLES", 0x05, 0x02, true },
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{ "PAGE_WALKS.CYCLES", 0x05, 0x03, true },
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{ "UOPS_ISSUED.ANY", 0x0E, 0x00, true },
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{ "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", 0x13, 0x02, true },
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{ "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", 0x13, 0x04, true },
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{ "LONGEST_LAT_CACHE.REFERENCE", 0x2E, 0x4F, true },
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{ "LONGEST_LAT_CACHE.MISS", 0x2E, 0x41, true },
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{ "L2_REJECT_XQ.ALL", 0x30, 0x00, true },
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{ "CORE_REJECT_L2Q.ALL", 0x31, 0x00, true },
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{ "CPU_CLK_UNHALTED.CORE_P", 0x3C, 0x00, true },
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{ "CPU_CLK_UNHALTED.REF", 0x3C, 0x01, true },
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{ "DL1.DIRTY_EVICTION", 0x51, 0x01, true },
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{ "ICACHE.HIT", 0x80, 0x01, true },
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{ "ICACHE.MISSES", 0x80, 0x02, true },
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{ "ICACHE.ACCESSES", 0x80, 0x03, true },
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{ "ITLB.MISS", 0x81, 0x04, true },
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{ "FETCH_STALL.ALL", 0x86, 0x00, true },
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{ "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", 0x86, 0x01, true },
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{ "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", 0x86, 0x02, true },
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{ "UOPS_NOT_DELIVERED.ANY", 0x9C, 0x00, true },
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{ "OFFCORE_RESPONSE.0", 0xB7, 0x01, true },
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{ "OFFCORE_RESPONSE.1", 0xB7, 0x02, true },
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{ "INST_RETIRED.ANY_P", 0xC0, 0x00, true },
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{ "UOPS_RETIRED.ANY", 0xC2, 0x00, true },
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{ "UOPS_RETIRED.MS", 0xC2, 0x01, true },
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{ "UOPS_RETIRED.FPDIV", 0xC2, 0x08, true },
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{ "UOPS_RETIRED.IDIV", 0xC2, 0x10, true },
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{ "MACHINE_CLEARS.SMC", 0xC3, 0x01, true },
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{ "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
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{ "MACHINE_CLEARS.FP_ASSIST", 0xC3, 0x04, true },
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{ "MACHINE_CLEARS.DISAMBIGUATION", 0xC3, 0x08, true },
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{ "MACHINE_CLEARS.ALL", 0xC3, 0x00, true },
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{ "BR_INST_RETIRED.ALL_BRANCHES", 0xC4, 0x00, true },
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{ "BR_INST_RETIRED.JCC", 0xC4, 0x7E, true },
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{ "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", 0xC4, 0x80, true },
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{ "BR_INST_RETIRED.TAKEN_JCC", 0xC4, 0xFE, true },
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{ "BR_INST_RETIRED.CALL", 0xC4, 0xF9, true },
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{ "BR_INST_RETIRED.REL_CALL", 0xC4, 0xFD, true },
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{ "BR_INST_RETIRED.IND_CALL", 0xC4, 0xFB, true },
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{ "BR_INST_RETIRED.RETURN", 0xC4, 0xF7, true },
|
|
|
|
|
{ "BR_INST_RETIRED.NON_RETURN_IND", 0xC4, 0xEB, true },
|
|
|
|
|
{ "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0xBF, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.ALL_BRANCHES", 0xC5, 0x00, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.JCC", 0xC5, 0x7E, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.TAKEN_JCC", 0xC5, 0xFE, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.IND_CALL", 0xC5, 0xFB, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.RETURN", 0xC5, 0xF7, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.NON_RETURN_IND", 0xC5, 0xEB, true },
|
|
|
|
|
{ "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", 0xCA, 0x01, true },
|
|
|
|
|
{ "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", 0xCA, 0x02, true },
|
|
|
|
|
{ "ISSUE_SLOTS_NOT_CONSUMED.ANY", 0xCA, 0x00, true },
|
|
|
|
|
{ "HW_INTERRUPTS.RECEIVED", 0xCB, 0x01, true },
|
|
|
|
|
{ "HW_INTERRUPTS.MASKED", 0xCB, 0x02, true },
|
|
|
|
|
{ "HW_INTERRUPTS.PENDING_AND_MASKED", 0xCB, 0x04, true },
|
|
|
|
|
{ "CYCLES_DIV_BUSY.ALL", 0xCD, 0x00, true },
|
|
|
|
|
{ "CYCLES_DIV_BUSY.IDIV", 0xCD, 0x01, true },
|
|
|
|
|
{ "CYCLES_DIV_BUSY.FPDIV", 0xCD, 0x02, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.ALL_LOADS", 0xD0, 0x81, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.ALL_STORES", 0xD0, 0x82, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.ALL", 0xD0, 0x83, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 0xD0, 0x11, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.DTLB_MISS_STORES", 0xD0, 0x12, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.DTLB_MISS", 0xD0, 0x13, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.LOCK_LOADS", 0xD0, 0x21, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.SPLIT_LOADS", 0xD0, 0x41, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.SPLIT_STORES", 0xD0, 0x42, true },
|
|
|
|
|
{ "MEM_UOPS_RETIRED.SPLIT", 0xD0, 0x43, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.L1_HIT", 0xD1, 0x01, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.L1_MISS", 0xD1, 0x08, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.L2_HIT", 0xD1, 0x02, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.L2_MISS", 0xD1, 0x10, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.HITM", 0xD1, 0x20, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.WCB_HIT", 0xD1, 0x40, true },
|
|
|
|
|
{ "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", 0xD1, 0x80, true },
|
|
|
|
|
{ "BACLEARS.ALL", 0xE6, 0x01, true },
|
|
|
|
|
{ "BACLEARS.RETURN", 0xE6, 0x08, true },
|
|
|
|
|
{ "BACLEAR.CONDS", 0xE6, 0x10, true },
|
|
|
|
|
{ "MS_DECODED.MS_ENTRY", 0xE7, 0x01, true },
|
|
|
|
|
{ "DECODED_RESTRICTION.PREDECODE_WRONG", 0xE9, 0x01, true },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table intel_goldmont = {
|
|
|
|
|
.tablename = "Intel Goldmont",
|
|
|
|
|
.names = intel_goldmont_names,
|
|
|
|
|
.nevents = sizeof(intel_goldmont_names) /
|
|
|
|
|
sizeof(struct name_to_event),
|
|
|
|
|
.next = NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table *
|
|
|
|
|
init_intel_goldmont(void)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
return &intel_goldmont;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-13 10:56:29 +03:00
|
|
|
/*
|
2018-07-14 10:54:04 +03:00
|
|
|
* Intel Skylake/Kabylake.
|
|
|
|
|
*
|
|
|
|
|
* The events that are not listed, because they are of little interest or
|
|
|
|
|
* require extra configuration:
|
|
|
|
|
* TX_*
|
|
|
|
|
* FRONTEND_RETIRED.*
|
|
|
|
|
* FP_ARITH_INST_RETIRED.*
|
|
|
|
|
* HLE_RETIRED.*
|
|
|
|
|
* RTM_RETIRED.*
|
|
|
|
|
* MEM_TRANS_RETIRED.*
|
|
|
|
|
* UOPS_DISPATCHED_PORT.*
|
2018-07-13 10:56:29 +03:00
|
|
|
*/
|
|
|
|
|
static struct name_to_event intel_skylake_kabylake_names[] = {
|
|
|
|
|
/* Event Name - Event Select - UMask */
|
2018-07-14 10:54:04 +03:00
|
|
|
{ "LD_BLOCKS.STORE_FORWARD", 0x03, 0x02, true },
|
|
|
|
|
{ "LD_BLOCKS.NO_SR", 0x03, 0x08, true },
|
|
|
|
|
{ "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", 0x07, 0x01, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", 0x08, 0x01, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", 0x08, 0x02, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", 0x08, 0x04, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", 0x08, 0x08, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.WALK_COMPLETED", 0x08, 0x0E, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.WALK_PENDING", 0x08, 0x10, true },
|
|
|
|
|
{ "DTLB_LOAD_MISSES.STLB_HIT", 0x08, 0x20, true },
|
|
|
|
|
{ "INT_MISC.RECOVERY_CYCLES", 0x0D, 0x01, true },
|
|
|
|
|
{ "INT_MISC.CLEAR_RESTEER_CYCLES", 0x0D, 0x80, true },
|
|
|
|
|
{ "UOPS_ISSUED.ANY", 0x0E, 0x01, true },
|
|
|
|
|
{ "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", 0x0E, 0x02, true },
|
|
|
|
|
{ "UOPS_ISSUED.SLOW_LEA", 0x0E, 0x20, true },
|
|
|
|
|
{ "L2_RQSTS.DEMAND_DATA_RD_MISS", 0x24, 0x21, true },
|
|
|
|
|
{ "L2_RQSTS.RFO_MISS", 0x24, 0x22, true },
|
|
|
|
|
{ "L2_RQSTS.CODE_RD_MISS", 0x24, 0x24, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_DEMAND_MISS", 0x24, 0x27, true },
|
|
|
|
|
{ "L2_RQSTS.PF_MISS", 0x24, 0x38, true },
|
|
|
|
|
{ "L2_RQSTS.MISS", 0x24, 0x3F, true },
|
|
|
|
|
{ "L2_RQSTS.DEMAND_DATA_RD_HIT", 0x24, 0x41, true },
|
|
|
|
|
{ "L2_RQSTS.RFO_HIT", 0x24, 0x42, true },
|
|
|
|
|
{ "L2_RQSTS.CODE_RD_HIT", 0x24, 0x44, true },
|
|
|
|
|
{ "L2_RQSTS.PF_HIT", 0x24, 0xD8, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_DEMAND_DATA_RD", 0x24, 0xE1, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_RFO", 0x24, 0xE2, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_CODE_RD", 0x24, 0xE4, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_DEMAND_REFERENCES", 0x24, 0xE7, true },
|
|
|
|
|
{ "L2_RQSTS.ALL_PF", 0x24, 0xF8, true },
|
|
|
|
|
{ "L2_RQSTS.REFERENCES", 0x24, 0xFF, true },
|
|
|
|
|
{ "SW_PREFETCH_ACCESS.NTA", 0x32, 0x01, true },
|
|
|
|
|
{ "SW_PREFETCH_ACCESS.T0", 0x32, 0x02, true },
|
|
|
|
|
{ "SW_PREFETCH_ACCESS.T1_T2", 0x32, 0x04, true },
|
|
|
|
|
{ "SW_PREFETCH_ACCESS.PREFETCHW", 0x32, 0x08, true },
|
|
|
|
|
{ "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
|
|
|
|
|
{ "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", 0x3C, 0x02, true },
|
|
|
|
|
{ "L1D_PEND_MISS.PENDING", 0x48, 0x01, true },
|
|
|
|
|
{ "L1D_PEND_MISS.FB_FULL", 0x48, 0x02, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", 0x49, 0x01, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.WALK_COMPLETED_4K", 0x49, 0x02, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", 0x49, 0x04, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.WALK_COMPLETED_1G", 0x49, 0x08, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.WALK_COMPLETED", 0x49, 0x0E, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.WALK_PENDING", 0x49, 0x10, true },
|
|
|
|
|
{ "DTLB_STORE_MISSES.STLB_HIT", 0x49, 0x20, true },
|
|
|
|
|
{ "LOAD_HIT_PRE.SW_PF", 0x4C, 0x01, true },
|
|
|
|
|
{ "EPT.WALK_PENDING", 0x4F, 0x10, true },
|
|
|
|
|
{ "L1D.REPLACEMENT", 0x51, 0x01, true },
|
|
|
|
|
{ "RS_EVENTS.EMPTY_CYCLES", 0x5E, 0x01, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", 0x60, 0x01, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", 0x60, 0x02, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", 0x60, 0x04, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", 0x60, 0x08, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", 0x60, 0x10, true },
|
|
|
|
|
{ "IDQ.MITE_UOPS", 0x79, 0x04, true },
|
|
|
|
|
{ "IDQ.DSB_UOPS", 0x79, 0x08, true },
|
|
|
|
|
{ "IDQ.MS_MITE_UOPS", 0x79, 0x20, true },
|
|
|
|
|
{ "IDQ.MS_UOPS", 0x79, 0x30, true },
|
|
|
|
|
{ "ICACHE_16B.IFDATA_STALL", 0x80, 0x04, true },
|
|
|
|
|
{ "ICACHE_64B.IFTAG_HIT", 0x83, 0x01, true },
|
|
|
|
|
{ "ICACHE_64B.IFTAG_MISS", 0x83, 0x02, true },
|
|
|
|
|
{ "ICACHE_64B.IFTAG_STALL", 0x83, 0x04, true },
|
|
|
|
|
{ "ITLB_MISSES.MISS_CAUSES_A_WALK", 0x85, 0x01, true },
|
|
|
|
|
{ "ITLB_MISSES.WALK_COMPLETED_4K", 0x85, 0x02, true },
|
|
|
|
|
{ "ITLB_MISSES.WALK_COMPLETED_2M_4M", 0x85, 0x04, true },
|
|
|
|
|
{ "ITLB_MISSES.WALK_COMPLETED_1G", 0x85, 0x08, true },
|
|
|
|
|
{ "ITLB_MISSES.WALK_COMPLETED", 0x85, 0x0E, true },
|
|
|
|
|
{ "ITLB_MISSES.WALK_PENDING", 0x85, 0x10, true },
|
|
|
|
|
{ "ITLB_MISSES.STLB_HIT", 0x85, 0x20, true },
|
|
|
|
|
{ "ILD_STALL.LCP", 0x87, 0x01, true },
|
|
|
|
|
{ "IDQ_UOPS_NOT_DELIVERED.CORE", 0x9C, 0x01, true },
|
|
|
|
|
{ "RESOURCE_STALLS.ANY", 0xA2, 0x01, true },
|
|
|
|
|
{ "RESOURCE_STALLS.SB", 0xA2, 0x08, true },
|
|
|
|
|
{ "EXE_ACTIVITY.EXE_BOUND_0_PORTS", 0xA6, 0x01, true },
|
|
|
|
|
{ "EXE_ACTIVITY.1_PORTS_UTIL", 0xA6, 0x02, true },
|
|
|
|
|
{ "EXE_ACTIVITY.2_PORTS_UTIL", 0xA6, 0x04, true },
|
|
|
|
|
{ "EXE_ACTIVITY.3_PORTS_UTIL", 0xA6, 0x08, true },
|
|
|
|
|
{ "EXE_ACTIVITY.4_PORTS_UTIL", 0xA6, 0x10, true },
|
|
|
|
|
{ "EXE_ACTIVITY.BOUND_ON_STORES", 0xA6, 0x40, true },
|
|
|
|
|
{ "LSD.UOPS", 0xA8, 0x01, true },
|
|
|
|
|
{ "DSB2MITE_SWITCHES.PENALTY_CYCLES", 0xAB, 0x02, true },
|
|
|
|
|
{ "ITLB.ITLB_FLUSH", 0xAE, 0x01, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.DEMAND_DATA_RD", 0xB0, 0x01, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.DEMAND_CODE_RD", 0xB0, 0x02, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.DEMAND_RFO", 0xB0, 0x04, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.ALL_DATA_RD", 0xB0, 0x08, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", 0xB0, 0x10, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS.ALL_REQUESTS", 0xB0, 0x80, true },
|
|
|
|
|
{ "UOPS_EXECUTED.THREAD", 0xB1, 0x01, true },
|
|
|
|
|
{ "UOPS_EXECUTED.CORE", 0xB1, 0x02, true },
|
|
|
|
|
{ "UOPS_EXECUTED.X87", 0xB1, 0x10, true },
|
|
|
|
|
{ "OFFCORE_REQUESTS_BUFFER.SQ_FULL", 0xB2, 0x01, true },
|
|
|
|
|
{ "TLB_FLUSH.DTLB_THREAD", 0xBD, 0x01, true },
|
|
|
|
|
{ "TLB_FLUSH.STLB_ANY", 0xBD, 0x20, true },
|
|
|
|
|
{ "INST_RETIRED.PREC_DIST", 0xC0, 0x01, true },
|
|
|
|
|
{ "OTHER_ASSISTS.ANY", 0xC1, 0x3F, true },
|
|
|
|
|
{ "UOPS_RETIRED.RETIRE_SLOTS", 0xC2, 0x02, true },
|
|
|
|
|
{ "MACHINE_CLEARS.MEMORY_ORDERING", 0xC3, 0x02, true },
|
|
|
|
|
{ "MACHINE_CLEARS.SMC", 0xC3, 0x04, true },
|
|
|
|
|
{ "BR_INST_RETIRED.CONDITIONAL", 0xC4, 0x01, true },
|
|
|
|
|
{ "BR_INST_RETIRED.NEAR_CALL", 0xC4, 0x02, true },
|
|
|
|
|
{ "BR_INST_RETIRED.NEAR_RETURN", 0xC4, 0x08, true },
|
|
|
|
|
{ "BR_INST_RETIRED.NOT_TAKEN", 0xC4, 0x10, true },
|
|
|
|
|
{ "BR_INST_RETIRED.NEAR_TAKEN", 0xC4, 0x20, true },
|
|
|
|
|
{ "BR_INST_RETIRED.FAR_BRANCH", 0xC4, 0x40, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.CONDITIONAL", 0xC5, 0x01, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.NEAR_CALL", 0xC5, 0x02, true },
|
|
|
|
|
{ "BR_MISP_RETIRED.NEAR_TAKEN", 0xC5, 0x20, true },
|
|
|
|
|
{ "HW_INTERRUPTS.RECEIVED", 0xCB, 0x01, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.STLB_MISS_LOADS", 0xD0, 0x11, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.STLB_MISS_STORES", 0xD0, 0x12, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.LOCK_LOADS", 0xD0, 0x21, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.SPLIT_LOADS", 0xD0, 0x41, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.SPLIT_STORES", 0xD0, 0x42, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.ALL_LOADS", 0xD0, 0x81, true },
|
|
|
|
|
{ "MEM_INST_RETIRED.ALL_STORES", 0xD0, 0x82, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L1_HIT", 0xD1, 0x01, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L2_HIT", 0xD1, 0x02, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L3_HIT", 0xD1, 0x04, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L1_MISS", 0xD1, 0x08, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L2_MISS", 0xD1, 0x10, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.L3_MISS", 0xD1, 0x20, true },
|
|
|
|
|
{ "MEM_LOAD_RETIRED.FB_HIT", 0xD1, 0x40, true },
|
|
|
|
|
{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", 0xD2, 0x01, true },
|
|
|
|
|
{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", 0xD2, 0x02, true },
|
|
|
|
|
{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", 0xD2, 0x04, true },
|
|
|
|
|
{ "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", 0xD2, 0x08, true },
|
|
|
|
|
{ "MEM_LOAD_MISC_RETIRED.UC", 0xD4, 0x04, true },
|
|
|
|
|
{ "BACLEARS.ANY", 0xE6, 0x01, true },
|
|
|
|
|
{ "L2_TRANS.L2_WB", 0xF0, 0x40, true },
|
|
|
|
|
{ "L2_LINES_IN.ALL", 0xF1, 0x1F, true },
|
|
|
|
|
{ "L2_LINES_OUT.SILENT", 0xF2, 0x01, true },
|
|
|
|
|
{ "L2_LINES_OUT.NON_SILENT", 0xF2, 0x02, true },
|
|
|
|
|
{ "L2_LINES_OUT.USELESS_HWPF", 0xF2, 0x04, true },
|
|
|
|
|
{ "SQ_MISC.SPLIT_LOCK", 0xF4, 0x10, true },
|
2018-07-13 10:56:29 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table intel_skylake_kabylake = {
|
|
|
|
|
.tablename = "Intel Skylake/Kabylake",
|
|
|
|
|
.names = intel_skylake_kabylake_names,
|
|
|
|
|
.nevents = sizeof(intel_skylake_kabylake_names) /
|
|
|
|
|
sizeof(struct name_to_event),
|
|
|
|
|
.next = NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table *
|
|
|
|
|
init_intel_skylake_kabylake(void)
|
|
|
|
|
{
|
|
|
|
|
return &intel_skylake_kabylake;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct event_table *
|
|
|
|
|
init_intel_generic(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
|
struct event_table *table;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* The kernel made sure the Architectural Version 1 PMCs were
|
|
|
|
|
* present.
|
|
|
|
|
*/
|
|
|
|
|
table = init_intel_arch1();
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now query the additional (non-architectural) events. They
|
|
|
|
|
* depend on the CPU model.
|
|
|
|
|
*/
|
|
|
|
|
eax = 0x01;
|
|
|
|
|
ebx = 0;
|
|
|
|
|
ecx = 0;
|
|
|
|
|
edx = 0;
|
|
|
|
|
x86_cpuid(&eax, &ebx, &ecx, &edx);
|
|
|
|
|
|
2018-07-13 12:53:42 +03:00
|
|
|
if (CPUID_TO_FAMILY(eax) == 6) {
|
|
|
|
|
switch (CPUID_TO_MODEL(eax)) {
|
2018-11-15 10:20:31 +03:00
|
|
|
case 0x37: /* Silvermont (Bay Trail) */
|
|
|
|
|
case 0x4A: /* Silvermont (Tangier) */
|
|
|
|
|
case 0x4C: /* Airmont (Braswell, Cherry Trail) */
|
|
|
|
|
case 0x4D: /* Silvermont (Avoton, Rangeley) */
|
|
|
|
|
case 0x5A: /* Silvermont (Anniedale) */
|
|
|
|
|
case 0x5D: /* Silvermont (SoFIA) */
|
|
|
|
|
table->next = init_intel_silvermont_airmont();
|
|
|
|
|
break;
|
2018-11-26 10:45:47 +03:00
|
|
|
case 0x5C: /* Goldmont (Apollo Lake) */
|
|
|
|
|
case 0x5F: /* Goldmont (Denvertion) */
|
|
|
|
|
table->next = init_intel_goldmont();
|
|
|
|
|
break;
|
2018-07-13 12:53:42 +03:00
|
|
|
case 0x4E: /* Skylake */
|
|
|
|
|
case 0x5E: /* Skylake */
|
|
|
|
|
case 0x8E: /* Kabylake */
|
|
|
|
|
case 0x9E: /* Kabylake */
|
|
|
|
|
table->next = init_intel_skylake_kabylake();
|
|
|
|
|
break;
|
|
|
|
|
}
|
2018-07-13 10:56:29 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return table;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* AMD Family 10h
|
|
|
|
|
*/
|
|
|
|
|
static struct name_to_event amd_f10h_names[] = {
|
2018-07-13 11:09:21 +03:00
|
|
|
{ "seg-load-all", 0x20, 0x7f, true },
|
|
|
|
|
{ "seg-load-es", 0x20, 0x01, true },
|
|
|
|
|
{ "seg-load-cs", 0x20, 0x02, true },
|
|
|
|
|
{ "seg-load-ss", 0x20, 0x04, true },
|
|
|
|
|
{ "seg-load-ds", 0x20, 0x08, true },
|
|
|
|
|
{ "seg-load-fs", 0x20, 0x10, true },
|
|
|
|
|
{ "seg-load-gs", 0x20, 0x20, true },
|
|
|
|
|
{ "seg-load-hs", 0x20, 0x40, true },
|
|
|
|
|
{ "l1cache-access", 0x40, 0x00, true },
|
|
|
|
|
{ "l1cache-miss", 0x41, 0x00, true },
|
|
|
|
|
{ "l1cache-refill", 0x42, 0x1f, true },
|
|
|
|
|
{ "l1cache-refill-invalid", 0x42, 0x01, true },
|
|
|
|
|
{ "l1cache-refill-shared", 0x42, 0x02, true },
|
|
|
|
|
{ "l1cache-refill-exclusive", 0x42, 0x04, true },
|
|
|
|
|
{ "l1cache-refill-owner", 0x42, 0x08, true },
|
|
|
|
|
{ "l1cache-refill-modified", 0x42, 0x10, true },
|
|
|
|
|
{ "l1cache-load", 0x43, 0x1f, true },
|
|
|
|
|
{ "l1cache-load-invalid", 0x43, 0x01, true },
|
|
|
|
|
{ "l1cache-load-shared", 0x43, 0x02, true },
|
|
|
|
|
{ "l1cache-load-exclusive", 0x43, 0x04, true },
|
|
|
|
|
{ "l1cache-load-owner", 0x43, 0x08, true },
|
|
|
|
|
{ "l1cache-load-modified", 0x43, 0x10, true },
|
|
|
|
|
{ "l1cache-writeback", 0x44, 0x1f, true },
|
|
|
|
|
{ "l1cache-writeback-invalid", 0x44, 0x01, true },
|
|
|
|
|
{ "l1cache-writeback-shared", 0x44, 0x02, true },
|
|
|
|
|
{ "l1cache-writeback-exclusive",0x44, 0x04, true },
|
|
|
|
|
{ "l1cache-writeback-owner", 0x44, 0x08, true },
|
|
|
|
|
{ "l1cache-writeback-modified", 0x44, 0x10, true },
|
|
|
|
|
{ "l1DTLB-hit-all", 0x4D, 0x07, true },
|
|
|
|
|
{ "l1DTLB-hit-4Kpage", 0x4D, 0x01, true },
|
|
|
|
|
{ "l1DTLB-hit-2Mpage", 0x4D, 0x02, true },
|
|
|
|
|
{ "l1DTLB-hit-1Gpage", 0x4D, 0x04, true },
|
|
|
|
|
{ "l1DTLB-miss-all", 0x45, 0x07, true },
|
|
|
|
|
{ "l1DTLB-miss-4Kpage", 0x45, 0x01, true },
|
|
|
|
|
{ "l1DTLB-miss-2Mpage", 0x45, 0x02, true },
|
|
|
|
|
{ "l1DTLB-miss-1Gpage", 0x45, 0x04, true },
|
|
|
|
|
{ "l2DTLB-miss-all", 0x46, 0x03, true },
|
|
|
|
|
{ "l2DTLB-miss-4Kpage", 0x46, 0x01, true },
|
|
|
|
|
{ "l2DTLB-miss-2Mpage", 0x46, 0x02, true },
|
2018-07-13 10:56:29 +03:00
|
|
|
/* l2DTLB-miss-1Gpage: reserved on some revisions, so disabled */
|
2018-07-13 11:09:21 +03:00
|
|
|
{ "l1ITLB-miss", 0x84, 0x00, true },
|
|
|
|
|
{ "l2ITLB-miss-all", 0x85, 0x03, true },
|
|
|
|
|
{ "l2ITLB-miss-4Kpage", 0x85, 0x01, true },
|
|
|
|
|
{ "l2ITLB-miss-2Mpage", 0x85, 0x02, true },
|
|
|
|
|
{ "mem-misalign-ref", 0x47, 0x00, true },
|
|
|
|
|
{ "ins-fetch", 0x80, 0x00, true },
|
|
|
|
|
{ "ins-fetch-miss", 0x81, 0x00, true },
|
|
|
|
|
{ "ins-refill-l2", 0x82, 0x00, true },
|
|
|
|
|
{ "ins-refill-sys", 0x83, 0x00, true },
|
|
|
|
|
{ "ins-fetch-stall", 0x87, 0x00, true },
|
|
|
|
|
{ "ins-retired", 0xC0, 0x00, true },
|
|
|
|
|
{ "ins-empty", 0xD0, 0x00, true },
|
|
|
|
|
{ "ops-retired", 0xC1, 0x00, true },
|
|
|
|
|
{ "branch-retired", 0xC2, 0x00, true },
|
|
|
|
|
{ "branch-miss-retired", 0xC3, 0x00, true },
|
|
|
|
|
{ "branch-taken-retired", 0xC4, 0x00, true },
|
|
|
|
|
{ "branch-taken-miss-retired", 0xC5, 0x00, true },
|
|
|
|
|
{ "branch-far-retired", 0xC6, 0x00, true },
|
|
|
|
|
{ "branch-resync-retired", 0xC7, 0x00, true },
|
|
|
|
|
{ "branch-near-retired", 0xC8, 0x00, true },
|
|
|
|
|
{ "branch-near-miss-retired", 0xC9, 0x00, true },
|
|
|
|
|
{ "branch-indirect-miss-retired", 0xCA, 0x00, true },
|
|
|
|
|
{ "int-hw", 0xCF, 0x00, true },
|
|
|
|
|
{ "int-cycles-masked", 0xCD, 0x00, true },
|
|
|
|
|
{ "int-cycles-masked-pending", 0xCE, 0x00, true },
|
|
|
|
|
{ "fpu-exceptions", 0xDB, 0x00, true },
|
|
|
|
|
{ "break-match0", 0xDC, 0x00, true },
|
|
|
|
|
{ "break-match1", 0xDD, 0x00, true },
|
|
|
|
|
{ "break-match2", 0xDE, 0x00, true },
|
|
|
|
|
{ "break-match3", 0xDF, 0x00, true },
|
2018-07-13 10:56:29 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table amd_f10h = {
|
|
|
|
|
.tablename = "AMD Family 10h",
|
|
|
|
|
.names = amd_f10h_names,
|
|
|
|
|
.nevents = sizeof(amd_f10h_names) /
|
|
|
|
|
sizeof(struct name_to_event),
|
|
|
|
|
.next = NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct event_table *
|
|
|
|
|
init_amd_f10h(void)
|
|
|
|
|
{
|
|
|
|
|
return &amd_f10h;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct event_table *
|
|
|
|
|
init_amd_generic(void)
|
|
|
|
|
{
|
|
|
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
|
|
|
|
|
|
eax = 0x01;
|
|
|
|
|
ebx = 0;
|
|
|
|
|
ecx = 0;
|
|
|
|
|
edx = 0;
|
|
|
|
|
x86_cpuid(&eax, &ebx, &ecx, &edx);
|
|
|
|
|
|
|
|
|
|
switch (CPUID_TO_FAMILY(eax)) {
|
|
|
|
|
case 0x10:
|
|
|
|
|
return init_amd_f10h();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* -------------------------------------------------------------------------- */
|
|
|
|
|
|
|
|
|
|
int
|
|
|
|
|
tprof_event_init(uint32_t ident)
|
|
|
|
|
{
|
|
|
|
|
switch (ident) {
|
|
|
|
|
case TPROF_IDENT_NONE:
|
|
|
|
|
return -1;
|
|
|
|
|
case TPROF_IDENT_INTEL_GENERIC:
|
|
|
|
|
cpuevents = init_intel_generic();
|
|
|
|
|
break;
|
|
|
|
|
case TPROF_IDENT_AMD_GENERIC:
|
|
|
|
|
cpuevents = init_amd_generic();
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
return (cpuevents == NULL) ? -1 : 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
recursive_event_list(struct event_table *table)
|
|
|
|
|
{
|
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
|
|
printf("%s:\n", table->tablename);
|
|
|
|
|
for (i = 0; i < table->nevents; i++) {
|
|
|
|
|
if (!table->names[i].enabled)
|
|
|
|
|
continue;
|
|
|
|
|
printf("\t%s\n", table->names[i].name);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (table->next != NULL) {
|
|
|
|
|
recursive_event_list(table->next);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
tprof_event_list(void)
|
|
|
|
|
{
|
|
|
|
|
recursive_event_list(cpuevents);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
recursive_event_lookup(struct event_table *table, const char *name,
|
|
|
|
|
struct tprof_param *param)
|
|
|
|
|
{
|
|
|
|
|
size_t i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < table->nevents; i++) {
|
|
|
|
|
if (!table->names[i].enabled)
|
|
|
|
|
continue;
|
|
|
|
|
if (!strcmp(table->names[i].name, name)) {
|
|
|
|
|
param->p_event = table->names[i].event;
|
|
|
|
|
param->p_unit = table->names[i].unit;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (table->next != NULL) {
|
|
|
|
|
recursive_event_lookup(table->next, name, param);
|
|
|
|
|
} else {
|
|
|
|
|
errx(EXIT_FAILURE, "event '%s' unknown", name);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
|
tprof_event_lookup(const char *name, struct tprof_param *param)
|
|
|
|
|
{
|
|
|
|
|
recursive_event_lookup(cpuevents, name, param);
|
|
|
|
|
}
|
