1996-03-11 23:56:48 +03:00
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/* $NetBSD: cpufunc.h,v 1.2 1996/03/11 20:56:50 phil Exp $ */
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1996-01-26 08:37:16 +03:00
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/*
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* Copyright (c) 1996 Matthias Pfaller.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matthias Pfaller.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NS532_CPUFUNC_H_
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#define _NS532_CPUFUNC_H_
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/*
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* Load a mmu register.
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*/
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#define lmr(reg, src) __asm __volatile("lmr " #reg ",%0" : : "g" (src))
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/*
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* Store a mmu register.
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*/
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#define smr(reg, dst) __asm __volatile("smr " #reg ",%0" : "=g" (dst) :)
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/*
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* Load the FPU status register.
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*/
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#define lfsr(src) __asm __volatile("lfsr %0" : : "g" (src))
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/*
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* Store the FPU status register.
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*/
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#define sfsr(src) __asm __volatile("sfsr %0" : "=g" (src) :)
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/*
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* Load a processor register.
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*/
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#define lprd(reg, src) __asm __volatile("lprd " #reg ",%0" : : "g" (src))
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#define lprw(reg, src) __asm __volatile("lprw " #reg ",%0" : : "g" (src))
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#define lprb(reg, src) __asm __volatile("lprb " #reg ",%0" : : "g" (src))
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/*
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* Store a processor register.
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*/
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#define sprd(reg, dst) __asm __volatile("sprd " #reg ",%0" : "=g" (dst) :)
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#define sprw(reg, dst) __asm __volatile("sprw " #reg ",%0" : "=g" ((short) (dst)) :)
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#define sprb(reg, dst) __asm __volatile("sprb " #reg ",%0" : "=g" ((char) (dst)) :)
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/*
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* Move data. This can be used to force
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* gcc to load a register variable.
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*/
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#define movd(src, dst) __asm __volatile("movd %1,%0" : "=g" (dst) : "g" (src))
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1996-03-11 23:56:48 +03:00
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/*
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* movs[bdw] for fast blockmoves.
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*/
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#define movs(type, from, to, n) do { \
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register int r0 __asm ("r0") = n; \
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register u_char *r1 __asm("r1") = from; \
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register u_char *r2 __asm("r2") = to; \
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__asm __volatile ("movs" type \
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: "=r" (r1), "=r" (r2) \
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: "0" (r1), "1" (r2), "r" (r0) \
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: "r0", "memory" \
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); \
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from = r1; to = r2; \
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} while (0)
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#define movsd(from, to, n) movs("d", from, to, n)
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#define movsw(from, to, n) movs("w", from, to, n)
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#define movsb(from, to, n) movs("b", from, to, n)
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/*
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* Invalidate data and/or instruction cache lines.
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*/
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#define cinv(mode, adr) __asm __volatile("cinv " #mode ",%0" : : "g" (adr))
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1996-01-26 08:37:16 +03:00
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/*
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* Load the ptb. This loads ptb0 and ptb1 to
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* avoid a cpu-bug when using dual address
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* space instructions.
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*/
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#define load_ptb(src) __asm __volatile("lmr ptb0,%0; lmr ptb1,%0" : : "g" (src))
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/*
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* Flush tlb. Just to be save this flushes
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* kernelmode and usermode translations.
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*/
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#define tlbflush() __asm __volatile("smr ptb0,r0; lmr ptb0,r0; lmr ptb1,r0" : : : "r0")
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/*
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* Bits in the cfg register.
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*/
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#define CFG_I 0x0001 /* Enable vectored interrupts */
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#define CFG_F 0x0002 /* Enable floating-point instruction set */
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#define CFG_M 0x0004 /* Enable memory management instruction set */
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#define CFG_ONE 0x00f0 /* Must be one */
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#define CFG_DE 0x0100 /* Enable direct exception mode */
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#define CFG_DC 0x0200 /* Enable data cache */
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#define CFG_LDC 0x0400 /* Lock data cache */
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#define CFG_IC 0x0800 /* Enable instruction cache */
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#define CFG_LIC 0x1000 /* Lock instruction cache */
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#define CFG_PF 0x2000 /* Enable pipelined floating-point execution */
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#endif /* !_NS532_CPUFUNC_H_ */
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