142 lines
5.1 KiB
Plaintext
142 lines
5.1 KiB
Plaintext
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Overview
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This is a port to the Motorola "SandPoint" evaluation system. The
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SandPoint is the successor to the "Yellowknife" system. The system
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can be fitted with different PMCs (Processor Mezzanine Cards). This
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port is specifically for the rev X2 motherboard system with the PPC
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8240 PMC rev X4 installed.
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All references (cf) listed here are for the MPC8240 Integrated Processor
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User's Manual.
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SandPoint Hardware Configuration
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This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC.
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This port assumes that the jumpers are set as follows:
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S3/S4 - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI
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slot toward near edge)
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S5 - Interrupt to PMC normal (switch toward near edge)
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S6 - Local I/O shared with slot 2 (switch toward near edge)
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Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts. The
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interrupts from the Winbond chip do not appear at the PMC.
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On the PPMC, we assume a 100MHz clock.
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on PPMC: (C == closed, or "on")
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SW2:
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C ROM on PCI bus (DINK32 on mainboard)
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- Map "B": CHRP
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C Motorola PPMC
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C Wait for initialization (peripheral mode)
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- Program mode: Normal mode
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- Select normal ROM
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- 33 MHz only
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- COP only resets local CPU/MPC107
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SW3:
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-C--C PCI 33, Mem 66, PPC 266
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-- 0.5 - 0.9 ns PCI hold time
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C 25 ohm PCI drive strength
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Address Map
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For this port, we choose the "Address Map B" (CHRP-compatible) for the
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system (see SW2, #2, above):
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(Processor View)
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0000 0000 0009 FFFF System Memory
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000A 0000 000F FFFF Compatibility Hole (programmable to go to PCI space
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or system memory--programmed for system memory--cf 5.8)
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0010 0000 3FFF FFFF System memory
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4000 0000 7FFF FFFF Reserved (programmed to give a memory select
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error if accessed--cf 5.7.2)
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8000 0000 FCFF FFFF PCI memory space
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FD00 0000 FDFF FFFF PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN)
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FE00 0000 FE7F FFFF PCI/ISA I/O space (Forwarded to PCI address space
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with high byte zeroed, but FE01 0000 and up are
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reserved)
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FE80 0000 FEBF FFFF PCI I/O space (Forwarded to PCI I/O space with high
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byte zeroed)
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FEC0 0000 FEDF FFFF PCI configuration address register (Each word in this
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range is aliased to the PCI CONFIG_ADDR register)
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FEE0 0000 FEEF FFFF PCI configuration data register (Each word in this
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range is aliased to the PCI CONFIG_DATA register)
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FEF0 0000 FEFF FFFF PCI interrupt acknowledge
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FF00 0000 FF7F FFFF 32- or 64-bit Flash/ROM space (Can hit either local
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memory or PCI bus -- cf. 5.6)
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FF80 0000 FFFF FFFF 8-, 32- or 64-bit Flash/ROM space (Can hit either
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local memory or PCI bus -- cf. 5.6)
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This is a host-mode port, so the inbound and output translation windows
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are unused.
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The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end
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of the PCI memory space: FCF0 0000, so EUMBBAR is FCF0 0000, giving us
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Message unit (I2O) base : FCF0 0000 (cf. 10.2, 10.2.3, 10.3)
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DMA base : FCF0 1000 (cf. 9.2)
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ATU base : FCF0 2000 (cf. 4.3.3)
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I2C base : FCF0 3000 (cf. 11.3)
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EPIC base : FCF4 0000 (cf. 12.2)
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Boot Information
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The SandPoint ships with the Motorola DINK32 ROM. This is a rather
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basic ROM with only serial-download (S-Record) capability for
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loading the kernel. Basically, the kernel is loaded to a specified
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address and you jump to it. The ROM takes care of initializing
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the MICRs and MCCRs. There is really no boot information to pass.
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It would be nice to have a much more complete ROM interface, allowing
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settings for, say, bootp/tftp boot, automatic boot, and persistent
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settings (for console rate, auto boot, bootp, etc), and that might
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be provided at some point, but that's not available as of this
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writing.
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So, the kernel is hard-coded to boot w/ 64MB for now.
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Interrupt Configuration
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The 8240 has the internal EPIC. For the SandPoint, the EPIC is programmed
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in mixed-mode (GCR) with direct interrupts (EICR). With this configuration,
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there are 13 available interrupts:
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4 global timers
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5 direct IRQs
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IRQ0 - PCI Slot #0 INTA#
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IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O
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IRQ2 - PCI Slot #2 INTA#
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IRQ3 - PCI Slot #3 INTA#
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IRQ4 - On-PPMC 16552 interrupt (Unity X2)
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IRQ4 - pulled down w/ resistor (Unity X4)
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4 internal interrupts
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I2C
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DMA Ch0
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DMA Ch1
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I2O message unit
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The SandPoint can run in one of 4 interrupt modes:
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0 - PMC host with IDE (3.3v PCI slots are unavailable)
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1 - PMC host w/o IDE (all PCI slots are available)
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2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC
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3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot
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We choose to run in mode 1 as Motorola recommends modes 0 or 1 for
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all new development. Unfortunately, mode 0 does not appear to
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work--"ISA" interrupts are lost. In this mode, with interrupts
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routed to PCI slot 3, we have to check for both a Winbond (ISA)
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interrupt, and a PCI slot interrupt. So basically, we have a
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two-level interrupt configuration for Winbond interrupts. The ISA
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bus attachment registers an interrupt for PCI slot 3 with its own
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interrupt handler. Drivers for ISA devices on the Winbond will
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register interrupts with the ISA interrupt handler. The sticky
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part of this is how to deal with one global interrupt priority.
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