330 lines
9.9 KiB
C
330 lines
9.9 KiB
C
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/* $NetBSD: scifreg.h,v 1.1 1999/09/13 10:31:22 itojun Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_SCIFREG_H_
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#define _SH3_SCIFREG_H_
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#ifndef BYTE_ORDER
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#error Define BYTE_ORDER!
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#endif
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/*
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* Serial Communication Interface (SCIF)
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*/
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#if !defined(SH4)
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/* SH3 definitions */
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/* Serial Mode Register */
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typedef union {
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unsigned char BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 7..0 */
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unsigned char CA :1;
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unsigned char CHR :1;
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unsigned char PE :1;
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unsigned char OE :1;
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unsigned char STOP:1;
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unsigned char MP :1;
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unsigned char CKS :2;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..7 */
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unsigned char CKS :2;
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unsigned char MP :1;
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unsigned char STOP:1;
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unsigned char OE :1;
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unsigned char PE :1;
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unsigned char CHR :1;
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unsigned char CA :1;
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#endif
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} BIT;
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} SH3SCSMR;
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/* Serial Control Register */
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typedef union {
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unsigned char BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 7..0 */
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unsigned char TIE :1;
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unsigned char RIE :1;
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unsigned char TE :1;
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unsigned char RE :1;
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unsigned char MPIE:1;
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unsigned char TEIE:1;
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unsigned char CKE :2;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..7 */
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unsigned char CKE :2;
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unsigned char TEIE:1;
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unsigned char MPIE:1;
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unsigned char RE :1;
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unsigned char TE :1;
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unsigned char RIE :1;
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unsigned char TIE :1;
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#endif
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} BIT;
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} SH3SCSCR;
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/* Serial Status Register */
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typedef union {
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unsigned char BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 7..0 */
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unsigned char TDRE:1;
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unsigned char RDRF:1;
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unsigned char ORER:1;
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unsigned char FER :1;
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unsigned char PER :1;
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unsigned char TEND:1;
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unsigned char MPB :1;
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unsigned char MPBT:1;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..7 */
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unsigned char MPBT:1;
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unsigned char MPB :1;
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unsigned char TEND:1;
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unsigned char PER :1;
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unsigned char FER :1;
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unsigned char ORER:1;
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unsigned char RDRF:1;
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unsigned char TDRE:1;
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#endif
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} BIT;
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} SH3SCSSR;
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#define SHREG_SCSMR2 (*(volatile unsigned char *) 0xa4000150)
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#define SHREG_SCBRR2 (*(volatile unsigned char *) 0xa4000152)
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#define SHREG_SCSCR2 (*(volatile unsigned char *) 0xa4000154)
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#define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xa4000156)
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#define SHREG_SCSSR2 (*(volatile unsigned short *) 0xa4000158)
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#define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xa400015A)
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#define SHREG_SCFCR2 (*(volatile unsigned char *) 0xa400015C)
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#define SHREG_SCFDR2 (*(volatile unsigned short *) 0xa400015E)
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#define SCSCR2_TIE 0x80 /* Transmit Interrupt Enable */
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#define SCSCR2_RIE 0x40 /* Recieve Interrupt Enable */
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#define SCSCR2_TE 0x20 /* Transmit Enable */
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#define SCSCR2_RE 0x10 /* Receive Enable */
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#define SCSCR2_CKE1 0x02 /* ClocK Enable 1 */
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#define SCSCR2_CKE0 0x01 /* ClocK Enable 0 */
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#define SCSSR2_ER 0x0080 /* ERror */
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#define SCSSR2_TEND 0x0040 /* Transmit END */
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#define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */
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#define SCSSR2_BRK 0x0010 /* BReaK detection */
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#define SCSSR2_FER 0x0008 /* Framing ERror */
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#define SCSSR2_PER 0x0004 /* Parity ERror */
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#define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */
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#define SCSSR2_DR 0x0001 /* Data Ready */
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#define SCFCR2_RTRG1 0x80 /* Receive TRiGger 1 */
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#define SCFCR2_RTRG0 0x40 /* Receive TRiGger 0 */
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#define SCFCR2_TTRG1 0x20 /* Transmit TRiGger 1 */
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#define SCFCR2_TTRG0 0x10 /* Transmit TRiGger 0 */
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#define SCFCR2_MCE 0x08 /* Modem Control Enable */
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#define SCFCR2_TFRST 0x04 /* Transmit Fifo register ReSeT */
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#define SCFCR2_RFRST 0x02 /* Receive Fifo register ReSeT */
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#define SCFCR2_LOOP 0x01 /* LOOP back test */
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#define FIFO_RCV_TRIGGER_1 0x00
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#define FIFO_RCV_TRIGGER_4 0x40
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#define FIFO_RCV_TRIGGER_8 0x80
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#define FIFO_RCV_TRIGGER_14 0xc0
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#define FIFO_XMT_TRIGGER_8 0x00
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#define FIFO_XMT_TRIGGER_4 0x10
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#define FIFO_XMT_TRIGGER_2 0x20
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#define FIFO_XMT_TRIGGER_1 0x30
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#else
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/* SH4 definitions */
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/* Serial Mode Register */
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typedef union {
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unsigned short BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned short :8;
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unsigned short CA :1;
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unsigned short CHR :1;
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unsigned short PE :1;
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unsigned short OE :1;
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unsigned short STOP :1;
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unsigned short MP :1;
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unsigned short CKS :2;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned short CKS :2;
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unsigned short MP :1;
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unsigned short STOP :1;
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unsigned short OE :1;
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unsigned short PE :1;
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unsigned short CHR :1;
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unsigned short CA :1;
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unsigned short :8;
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#endif
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} BIT;
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} SH3SCSMR;
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/* Serial Control Register */
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typedef union {
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unsigned short BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned short :8;
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unsigned short TIE :1;
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unsigned short RIE :1;
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unsigned short TE :1;
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unsigned short RE :1;
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unsigned short REIE :1;
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unsigned short :1;
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unsigned short CKE1 :1;
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unsigned short :1;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned short :1;
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unsigned short CKE1 :1;
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unsigned short :1;
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unsigned short REIE :1;
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unsigned short RE :1;
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unsigned short TE :1;
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unsigned short RIE :1;
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unsigned short TIE :1;
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unsigned short :8;
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#endif
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} BIT;
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} SH3SCSCR;
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/* Serial Status Register */
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typedef union {
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unsigned short BYTE; /* Byte Access */
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struct { /* Bit Access */
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#if BYTE_ORDER == BIG_ENDIAN
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/* Bit 15..0 */
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unsigned short PER3 :1;
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unsigned short PER2 :1;
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unsigned short PER1 :1;
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unsigned short PER0 :1;
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unsigned short FER3 :1;
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unsigned short FER2 :1;
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unsigned short FER1 :1;
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unsigned short FER0 :1;
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unsigned short ER :1;
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unsigned short TEND :1;
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unsigned short TDFE :1;
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unsigned short BRK :1;
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unsigned short FER :1;
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unsigned short PER :1;
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unsigned short RDF :1;
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unsigned short DR :1;
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#else /* BYTE_ORDER == LITTLE_ENDIAN */
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/* Bit 0..15 */
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unsigned short DR :1;
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unsigned short RDF :1;
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unsigned short PER :1;
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unsigned short FER :1;
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unsigned short BRK :1;
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unsigned short TDFE :1;
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unsigned short TEND :1;
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unsigned short ER :1;
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unsigned short FER0 :1;
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unsigned short FER1 :1;
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unsigned short FER2 :1;
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unsigned short FER3 :1;
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unsigned short PER0 :1;
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unsigned short PER1 :1;
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unsigned short PER2 :1;
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unsigned short PER3 :1;
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#endif
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} BIT;
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} SH3SCSSR;
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#define SHREG_SCSMR2 (*(volatile unsigned short *) 0xffe80000)
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#define SHREG_SCBRR2 (*(volatile unsigned char *) 0xffe80004)
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#define SHREG_SCSCR2 (*(volatile unsigned short *) 0xffe80008)
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#define SHREG_SCFTDR2 (*(volatile unsigned char *) 0xffe8000c)
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#define SHREG_SCFSR2 (*(volatile unsigned short *) 0xffe80010)
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#define SHREG_SCFRDR2 (*(volatile unsigned char *) 0xffe80014)
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#define SHREG_SCFCR2 (*(volatile unsigned short *) 0xffe80018)
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#define SHREG_SCFDR2 (*(volatile unsigned short *) 0xffe8001c)
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#define SHREG_SCSPTR2 (*(volatile unsigned short *) 0xffe80020)
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#define SHREG_SCLSR2 (*(volatile unsigned short *) 0xffe80024)
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/* alias */
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#define SHREG_SCSFDR2 SHREG_SCFTDR2
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#define SHREG_SCSSR2 SHREG_SCFSR2
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#define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */
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#define SCSCR2_RIE 0x0040 /* Recieve Interrupt Enable */
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#define SCSCR2_TE 0x0020 /* Transmit Enable */
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#define SCSCR2_RE 0x0010 /* Receive Enable */
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#define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */
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#define SCSSR2_ER 0x0080 /* ERror */
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#define SCSSR2_TEND 0x0040 /* Transmit END */
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#define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */
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#define SCSSR2_BRK 0x0010 /* BReaK detection */
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#define SCSSR2_FER 0x0008 /* Framing ERror */
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#define SCSSR2_PER 0x0004 /* Parity ERror */
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#define SCSSR2_RDF 0x0002 /* Recieve fifo Data Full */
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#define SCSSR2_DR 0x0001 /* Data Ready */
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#define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */
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#define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */
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#define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */
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#define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */
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#define SCFCR2_MCE 0x0008 /* Modem Control Enable */
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#define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */
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#define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */
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#define SCFCR2_LOOP 0x0001 /* LOOP back test */
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#define FIFO_RCV_TRIGGER_1 0x0000
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#define FIFO_RCV_TRIGGER_4 0x0040
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#define FIFO_RCV_TRIGGER_8 0x0080
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#define FIFO_RCV_TRIGGER_14 0x00c0
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#define FIFO_XMT_TRIGGER_8 0x0000
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#define FIFO_XMT_TRIGGER_4 0x0010
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#define FIFO_XMT_TRIGGER_2 0x0020
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#define FIFO_XMT_TRIGGER_1 0x0030
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#endif
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/* common definitions */
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#define SCFDR2_TXCNT 0xff00 /* Tx CouNT */
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#define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */
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#define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */
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#define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */
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#endif /* !_SH3_SCIFREG_ */
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