196 lines
6.4 KiB
C
196 lines
6.4 KiB
C
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/* $NetBSD: spifireg.h,v 1.1 2000/10/30 10:07:35 tsubai Exp $ */
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/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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struct spifi_reg {
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volatile int spstat; /* RO: SPIFI state */
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volatile int cmlen; /* RW: Command/message length */
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volatile int cmdpage; /* RW: Command page */
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volatile int count_hi; /* RW: Data count (high) */
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volatile int count_mid; /* RW: (mid) */
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volatile int count_low; /* RW: (low) */
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volatile int svptr_hi; /* RO: Saved data pointer (high)*/
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volatile int svptr_mid; /* RO: (mid) */
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volatile int svptr_low; /* RO: (low) */
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volatile int intr; /* RW: Processor interrupt */
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volatile int imask; /* RW: Processor interrupt mask */
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volatile int prctrl; /* RW: Processor control */
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volatile int prstat; /* RO: Processor status */
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volatile int init_status; /* RO: Initiator status */
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volatile int fifoctrl; /* RW: FIFO control */
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volatile int fifodata; /* RW: FIFO data */
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volatile int config; /* RW: Configuration */
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volatile int data_xfer; /* RW: Data transfer */
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volatile int autocmd; /* RW: Auto command control */
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volatile int autostat; /* RW: Auto status control */
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volatile int resel; /* RW: Reselection */
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volatile int select; /* RW: Selection */
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volatile int prcmd; /* WO: Processor command */
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volatile int auxctrl; /* RW: Aux control */
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volatile int autodata; /* RW: Auto data control */
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volatile int loopctrl; /* RW: Loopback control */
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volatile int loopdata; /* RW: Loopback data */
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volatile int identify; /* WO: Identify (?) */
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volatile int complete; /* WO: Command complete (?) */
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volatile int scsi_status; /* WO: SCSI status (?) */
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volatile int data; /* RW: Data register (?) */
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volatile int icond; /* RO: Interrupt condition */
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volatile int fastwide; /* RW: Fast/wide enable */
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volatile int exctrl; /* RW: Extended control */
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volatile int exstat; /* RW: Extended status */
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volatile int test; /* RW: SPIFI test register */
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volatile int quematch; /* RW: Queue match */
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volatile int quecode; /* RW: Queue code */
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volatile int quetag; /* RW: Queue tag */
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volatile int quepage; /* RW: Queue page */
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int image[88]; /* (image of the above) */
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struct {
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volatile int cdb[12]; /* RW: Command descriptor block */
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volatile int quecode; /* RW: Queue code */
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volatile int quetag; /* RW: Queue tag */
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volatile int idmsg; /* RW: Identify message */
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volatile int status; /* RW: SCSI status */
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} cmbuf[8];
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};
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/* spstat */
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#define SPS_IDLE 0x00
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#define SPS_SEL 0x01
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#define SPS_ARB 0x02
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#define SPS_RESEL 0x03
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#define SPS_MSGOUT 0x04
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#define SPS_COMMAND 0x05
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#define SPS_DISCON 0x06
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#define SPS_NXIN 0x07
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#define SPS_INTR 0x08
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#define SPS_NXOUT 0x09
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#define SPS_CCOMP 0x0a
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#define SPS_SVPTR 0x0b
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#define SPS_STATUS 0x0c
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#define SPS_MSGIN 0x0d
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#define SPS_DATAOUT 0x0e
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#define SPS_DATAIN 0x0f
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/* cmlen */
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#define CML_LENMASK 0x0f
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#define CML_AMSG_EN 0x40
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#define CML_ACOM_EN 0x80
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/* intr and imask */
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#define INTR_BSRQ 0x01
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#define INTR_COMRECV 0x02
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#define INTR_PERR 0x04
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#define INTR_TIMEO 0x08
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#define INTR_DERR 0x10
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#define INTR_TGSEL 0x20
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#define INTR_DISCON 0x40
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#define INTR_FCOMP 0x80
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#define INTR_BITMASK \
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"\20\10FCOMP\07DISCON\06TGSEL\05DERR\04TIMEO\03PERR\02COMRECV\01BSRQ"
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/* prstat */
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#define PRS_IO 0x08
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#define PRS_CD 0x10
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#define PRS_MSG 0x20
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#define PRS_ATN 0x40
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#define PRS_Z 0x80
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#define PRS_PHASE (PRS_MSG | PRS_CD | PRS_IO)
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#define PRS_BITMASK "\20\10Z\07ATN\06MSG\05CD\04IO"
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/* init_status */
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#define IST_ACK 0x40
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/* fifoctrl */
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#define FIFOC_FSLOT 0x0f /* Free slots in FIFO */
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#define FIFOC_SSTKACT 0x10 /* Synchronous stack active (?) */
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#define FIFOC_RQOVRN 0x20
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#define FIFOC_CLREVEN 0x00
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#define FIFOC_CLRODD 0x40
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#define FIFOC_FLUSH 0x80
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#define FIFOC_LOAD 0xc0
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/* config */
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#define CONFIG_PGENEN 0x08 /* Parity generation enable */
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#define CONFIG_PCHKEN 0x10 /* Parity checking enable */
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#define CONFIG_WORDEN 0x20
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#define CONFIG_AUTOID 0x40
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#define CONFIG_DMABURST 0x80
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/* select */
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#define SEL_SETATN 0x02
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#define SEL_IRESELEN 0x04
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#define SEL_ISTART 0x08
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#define SEL_WATN 0x80
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/* prcmd */
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#define PRC_DATAOUT 0
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#define PRC_DATAIN 1
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#define PRC_COMMAND 2
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#define PRC_STATUS 3
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#define PRC_TRPAD 4
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#define PRC_MSGOUT 6
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#define PRC_MSGIN 7
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#define PRC_KILLREQ 0x08
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#define PRC_CLRACK 0x10
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#define PRC_NJMP 0x80
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/* auxctrl */
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#define AUXCTRL_DMAEDGE 0x04
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#define AUXCTRL_SETRST 0x20 /* Bus reset (?) */
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#define AUXCTRL_CRST 0x40
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#define AUXCTRL_SRST 0x80
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/* autodata */
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#define ADATA_IN 0x40
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#define ADATA_EN 0x80
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/* icond */
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#define ICOND_ADATAOFF 0x02
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#define ICOND_AMSGOFF 0x06
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#define ICOND_ACMDOFF 0x0a
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#define ICOND_ASTATOFF 0x0e
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#define ICOND_SVPTEXP 0x10
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#define ICOND_ADATAMIS 0x20
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#define ICOND_CNTZERO 0x40
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#define ICOND_UXPHASEZ 0x80
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#define ICOND_UXPHASENZ 0x81
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#define ICOND_NXTREQ 0xa0
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#define ICOND_UKMSGZ 0xc0
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#define ICOND_UKMSGNZ 0xc1
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#define ICOND_UBF 0xe0 /* Unexpected bus free */
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/* fastwide */
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#define FAST_FASTEN 0x01
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/* exctrl */
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#define EXC_IPLOCK 0x04 /* Initiator page lock */
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/* exstat */
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#define EXS_UBF 0x08 /* Unexpected bus free */
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