110 lines
4.7 KiB
C
110 lines
4.7 KiB
C
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/* $NetBSD: pciide_piix_reg.h,v 1.2 1998/10/12 16:09:21 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for Intel's PIIX serie PCI IDE controllers.
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* See Intel's
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* "82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE XCELERATOR" and
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* "82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)"
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* available from http://www.intel.com/
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*/
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/*
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* Bus master interface base address register
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*/
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#define PIIX_BMIBA 0x20
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#define PIIX_BMIBA_ADDR(x) (x & 0x0000FFFF0)
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#define PIIX_BMIBA_RTE(x) (x & 0x000000001)
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#define PIIX_BMIBA_RTE_IO 0x000000001 /* base addr maps to I/O space */
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/*
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* IDE timing register
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* 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
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*/
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#define PIIX_IDETIM 0x40
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#define PIIX_IDETIM_READ(x, channel) (((x) >> (16 * (channel))) & 0x0000FFFF)
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#define PIIX_IDETIM_SET(x, bytes, channel) \
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((x) | ((bytes) << (16 * (channel))))
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#define PIIX_IDETIM_CLEAR(x, bytes, channel) \
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((x) & ~((bytes) << (16 * (channel))))
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#define PIIX_IDETIM_IDE 0x8000 /* PIIX decode IDE registers */
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#define PIIX_IDETIM_SITRE 0x4000 /* slaves IDE timing registers
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enabled (PIIX3/4 only) */
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#define PIIX_IDETIM_ISP_MASK 0x3000 /* IOrdy sample point */
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#define PIIX_IDETIM_ISP_SHIFT 12
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#define PIIX_IDETIM_ISP_SET(x) ((x) << PIIX_IDETIM_ISP_SHIFT)
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#define PIIX_IDETIM_RTC_MASK 0x0300 /* recovery time */
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#define PIIX_IDETIM_RTC_SHIFT 8
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#define PIIX_IDETIM_RTC_SET(x) ((x) << PIIX_IDETIM_RTC_SHIFT)
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#define PIIX_IDETIM_DTE(d) (0x0008 << (4 * (d))) /* DMA timing only */
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#define PIIX_IDETIM_PPE(d) (0x0004 << (4 * (d))) /* prefetch/posting */
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#define PIIX_IDETIM_IE(d) (0x0002 << (4 * (d))) /* IORDY enable */
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#define PIIX_IDETIM_TIME(d) (0x0001 << (4 * (d))) /* Fast timing enable */
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/*
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* Slave IDE timing register (PIIX3/4 only)
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* This register must be enabled via the PIIX_IDETIM_SITRE bit
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*/
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#define PIIX_SIDETIM 0x44
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#define PIIX_SIDETIM_ISP_MASK(channel) (0x0c << ((channel) * 4))
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#define PIIX_SIDETIM_ISP_SHIFT 2
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#define PIIX_SIDETIM_ISP_SET(x, channel) \
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(x << (PIIX_SIDETIM_ISP_SHIFT + ((channel) * 4)))
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#define PIIX_SIDETIM_RTC_MASK(channel) (0x03 << ((channel) * 4))
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#define PIIX_SIDETIM_RTC_SHIFT 0
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#define PIIX_SIDETIM_RTC_SET(x, channel) \
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(x << (PIIX_SIDETIM_RTC_SHIFT + ((channel) * 4)))
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/*
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* Ultra DMA/33 register (PIIX4 only)
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*/
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#define PIIX_UDMAREG 0x48
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/* Control register */
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#define PIIX_UDMACTL_DRV_EN(channel, drive) (0x01 << ((channel) * 2 + (drive)))
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/* Ultra DMA/33 timing register (PIIX4 only) */
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#define PIIX_UDMATIM_SHIFT 16
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#define PIIX_UDMATIM_SET(x, channel, drive) \
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(((x) << ((channel * 8) + (drive * 4))) << PIIX_UDMATIM_SHIFT)
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/*
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* these tables define the differents values to upload to the
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* ISP and RTC registers for the various PIO and DMA mode
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* (from the PIIX4 doc).
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*/
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static int8_t piix_isp_pio[] = {0x00, 0x00, 0x01, 0x02, 0x02};
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static int8_t piix_rtc_pio[] = {0x00, 0x00, 0x00, 0x01, 0x03};
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static int8_t piix_isp_dma[] = {0x00, 0x02, 0x02};
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static int8_t piix_rtc_dma[] = {0x00, 0x02, 0x03};
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static int8_t piix4_sct_udma[] = {0x00, 0x01, 0x02};
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