130 lines
4.0 KiB
C
130 lines
4.0 KiB
C
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/* $NetBSD: sioreg.h,v 1.1 1996/04/23 14:10:53 cgd Exp $ */
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/*
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* Copyright (c) 1996 BBN Corporation.
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* BBN Systems and Technologies Division
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* 10 Moulton Street
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* Cambridge, Ma. 02138
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* 617-873-3000
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this permission appear in all copies and in
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* supporting documentation, and that the name of BBN Corporation not be used
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* in advertising or publicity pertaining to distribution of the software
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* without specific, written prior permission. BBN makes no representations
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* about the suitability of this software for any purposes. It is provided
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* "AS IS" without express or implied warranties.
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*/
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/*
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* Intel 82378 System I/O (SIO) Chip
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*
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* Taken from the Intel "Peripheral Components" manual, 1995 Edition.
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*/
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/*
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* Device-specific PCI Configuration Registers
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*/
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/*
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* PCI Control Registers
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*/
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#define SIO_PCIREG_PCICON 0x40 /* PCI Control */
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#define SIO_PCIREG_PAC 0x41 /* PCI Arbiter Control */
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#define SIO_PCIREG_PAPC 0x42 /* PCI Arbiter Priority Control */
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#define SIO_PCIREG_ARBPRIX 0x43 /* PCI Arbiter Priority Control Ext. */
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/*
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* Memory Chip Select Registers
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*/
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#define SIO_PCIREG_MEMCSCON 0x44 /* MEMCS# Control */
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#define SIO_PCIREG_MEMCSBOH 0x45 /* MEMCS# Bottom of Hole */
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#define SIO_PCIREG_MEMCSTOH 0x46 /* MEMCS# Top of Hole */
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#define SIO_PCIREG_MEMCSTOM 0x47 /* MEMCS# Top of Memory */
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#define SIO_PCIREG_MAR1 0x54 /* MEMCS# Attribute 1 */
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#define SIO_PCIREG_MAR2 0x55 /* MEMCS# Attribute 2 */
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#define SIO_PCIREG_MAR3 0x56 /* MEMCS# Attribute 3 */
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#define SIO_PCIREG_DMASGRB 0x57 /* DMA Scatter/Gather Rel. Base Addr. */
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/*
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* ISA Address Decoder Registers
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*/
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#define SIO_PCIREG_IADCON 0x48 /* ISA Address Decoder Control */
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#define SIO_PCIREG_IADRBE 0x49 /* ISA Addr. Decoder ROM Block Enable */
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#define SIO_PCIREG_IADBOH 0x4A /* ISA Addr. Decoder Bottom of Hole */
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#define SIO_PCIREG_IADTOH 0x4B /* ISA Addr. Decoder Top of Hole */
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/*
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* Clocks and Timers
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*/
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#define SIO_PCIREG_ICRT 0x4C /* ISA Controller Recovery Timer */
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#define SIO_PCIREG_ICD 0x4D /* ISA Clock Divisor */
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#define SIO_PCIREG_ 0x80 /* BIOS Timer Base Address */
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#define SIO_PCIREG_CTLTMRL 0xAC /* Clock Throttle STPCLK# Low Timer */
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#define SIO_PCIREG_CTLTMRH 0xAE /* Clock Throttle STPCLK# High Timer */
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/*
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* Miscellaneous
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*/
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#define SIO_PCIREG_UBCSA 0x4E /* Utility Bus Chip Select A */
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#define SIO_PCIREG_UBCSB 0x4F /* Utility Bus Chip Select B */
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/*
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* PIRQ# Route Control
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*/
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#define SIO_PCIREG_PIRQ0 0x60 /* PIRQ0 Route Control */
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#define SIO_PCIREG_PIRQ1 0x61 /* PIRQ1 Route Control */
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#define SIO_PCIREG_PIRQ2 0x62 /* PIRQ2 Route Control */
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#define SIO_PCIREG_PIRQ3 0x63 /* PIRQ3 Route Control */
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#define SIO_PCIREG_PIRQ_RTCTRL SIO_PCIREG_PIRQ0
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/*
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* System Management Interrupt (SMI)
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*/
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#define SIO_PCIREG_SMICNTL 0xA0 /* SMI Control */
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#define SIO_PCIREG_SMIEN 0xA2 /* SMI Enable */
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#define SIO_PCIREG_SEE 0xA4 /* System Event Enable */
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#define SIO_PCIREG_FTMR 0xA8 /* Fast Off Timer */
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#define SIO_PCIREG_SMIREQ 0xAA /* SMI Request */
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/*
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* Non-Configuration Registers
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*/
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/*
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* Control
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*/
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#define SIO_REG_RSTUB 0x060 /* Reset UBus */
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#define SIO_REG_NMICTRL 0x061 /* NMI Status and Control */
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#define SIO_REG_CMOSRAM 0x070 /* CMOS RAM Address and NMI Mask */
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#define SIO_REG_NMIMASK 0x070 /* CMOS RAM Address and NMI Mask */
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#define SIO_REG_PORT92 0x092 /* Port 92 */
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#define SIO_REG_CPERR 0x0F0 /* Coprocessor Error */
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/*
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* Interrupt
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*/
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#define SIO_REG_ICU1 0x020 /* Intr. Controller #1 Control */
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#define SIO_REG_ICU1MASK 0x021 /* Intr. Controller #1 Mask */
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#define SIO_REG_ICU2 0x0A0 /* Intr. Controller #2 Control */
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#define SIO_REG_ICU2MASK 0x0A1 /* Intr. Controller #2 Mask */
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#define SIO_REG_ICU1ELC 0x4D0 /* #1's Edge/Level Control */
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#define SIO_REG_ICU2ELC 0x4D1 /* #2's Edge/Level Control */
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#define SIO_ICUSIZE 16 /* I/O Port Sizes */
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/*
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* Timer
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*/
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/* XXX need Timer definitions */
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/*
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* DMA
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*/
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/* XXX need DMA definitions */
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