1995-04-21 06:47:35 +04:00
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/* $NetBSD: scsi.c,v 1.14 1995/04/21 02:48:03 briggs Exp $ */
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1994-10-26 11:45:48 +03:00
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1994-01-30 04:08:50 +03:00
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/*
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1993-09-29 09:08:37 +03:00
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* Copyright (C) 1993 Allen K. Briggs, Chris P. Caputo,
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* Michael L. Finch, Bradley A. Grantham, and
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* Lawrence A. Kesteloot
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Alice Group.
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* 4. The names of the Alice Group or any of its members may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE ALICE GROUP ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE ALICE GROUP BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define PSEUDO_DMA 1
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1995-04-21 06:47:35 +04:00
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static int pdebug = 0;
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1993-09-29 09:08:37 +03:00
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1994-01-30 04:08:50 +03:00
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#include <sys/types.h>
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#include <sys/malloc.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/device.h>
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1994-11-29 06:43:52 +03:00
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#include <scsi/scsi_all.h>
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#include <scsi/scsi_debug.h>
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#include <scsi/scsiconf.h>
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1993-09-29 09:08:37 +03:00
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#include "scsi_defs.h"
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#define PAD(n) u_char n[15]
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1994-01-30 04:08:50 +03:00
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#include <machine/scsi_5380.h>
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1993-09-29 09:08:37 +03:00
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#undef PAD
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#define SCI_PHASE_DISC 0 /* sort of ... */
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#define SCI_CLR_INTR(regs) {register int temp = regs->sci_iack;}
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#define SCI_ACK(ptr,phase) (ptr)->sci_tcmd = (phase)
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#define SCSI_TIMEOUT_VAL 10000000
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1995-04-21 06:47:35 +04:00
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#define WAIT_FOR_NOT_REQ(ptr) { \
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int scsi_timeout = SCSI_TIMEOUT_VAL; \
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while ( ((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
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((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
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((ptr)->sci_bus_csr & SCI_BUS_REQ) && \
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(--scsi_timeout) ); \
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if (!scsi_timeout) { \
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printf("scsi timeout--WAIT_FOR_NOT_REQ---scsi.c, line %d.\n", \
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__LINE__); \
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goto scsi_timeout_error; \
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} \
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}
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#define WAIT_FOR_REQ(ptr) { \
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int scsi_timeout = SCSI_TIMEOUT_VAL; \
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while ( (((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
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(((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
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(((ptr)->sci_bus_csr & SCI_BUS_REQ) == 0) && \
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(--scsi_timeout) ); \
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if (!scsi_timeout) { \
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printf("scsi timeout--WAIT_FOR_REQ---scsi.c, line %d.\n", \
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__LINE__); \
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goto scsi_timeout_error; \
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} \
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}
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#define WAIT_FOR_BSY(ptr) { \
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int scsi_timeout = SCSI_TIMEOUT_VAL; \
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while ( (((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
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(((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
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(((ptr)->sci_bus_csr & SCI_BUS_BSY) == 0) && \
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(--scsi_timeout) ); \
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if (!scsi_timeout) { \
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printf("scsi timeout--WAIT_FOR_BSY---scsi.c, line %d.\n", \
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__LINE__); \
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goto scsi_timeout_error; \
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} \
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}
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1993-09-29 09:08:37 +03:00
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#ifdef DDB
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1995-04-21 06:47:35 +04:00
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int Debugger();
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1993-09-29 09:08:37 +03:00
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#else
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#define Debugger() panic("Should call Debugger here (mac/dev/scsi.c).")
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#endif
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1995-04-21 06:47:35 +04:00
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typedef unsigned long int physaddr;
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typedef sci_regmap_t sci_padded_regmap_t;
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1993-09-29 09:08:37 +03:00
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1994-01-30 04:08:50 +03:00
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#define NNCR5380 1
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1995-04-20 19:32:01 +04:00
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struct ncr5380_softc {
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1995-04-21 06:47:35 +04:00
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struct device sc_dev;
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1994-01-30 04:08:50 +03:00
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1995-04-21 06:47:35 +04:00
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void *reg_base;
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int adapter_target;
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struct scsi_link sc_link;
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1995-04-20 19:32:01 +04:00
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};
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1993-09-29 09:08:37 +03:00
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/* From Guide to Mac II family hardware, p. 137 */
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1994-06-26 17:00:32 +04:00
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/* These are "adjusted" in the init routine. */
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1995-04-21 06:47:35 +04:00
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static volatile sci_padded_regmap_t *ncr = (sci_regmap_t *) 0x10000;
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static volatile long *sci_4byte_addr = (long *) 0x6000;
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static volatile u_char *sci_1byte_addr = (u_char *) 0x12000;
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static unsigned int ncr5380_adapter_info(struct ncr5380_softc * ncr5380);
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static void ncr5380_minphys(struct buf * bp);
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static int ncr5380_scsi_cmd(struct scsi_xfer * xs);
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static int ncr5380_show_scsi_cmd(struct scsi_xfer * xs);
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static int ncr5380_reset_target(int adapter, int target);
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static int ncr5380_poll(int adapter, int timeout);
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static int ncr5380_send_cmd(struct scsi_xfer * xs);
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extern void ncr5380_intr(int adapter);
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extern void spinwait(int);
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static int
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scsi_gen(int adapter, int id, int lun,
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struct scsi_generic * cmd, int cmdlen,
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void *databuf, int datalen);
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static int
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scsi_group0(int adapter, int id, int lun,
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int opcode, int addr, int len,
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int flags, caddr_t databuf, int datalen);
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struct scsi_adapter ncr5380_switch = {
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ncr5380_scsi_cmd, /* scsi_cmd() */
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ncr5380_minphys, /* scsi_minphys() */
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0, /* open_target_lu() */
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0, /* close_target_lu() */
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1993-09-29 09:08:37 +03:00
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};
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1993-11-29 03:32:22 +03:00
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/* This is copied from julian's bt driver */
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/* "so we have a default dev struct for our link struct." */
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1994-06-26 17:00:32 +04:00
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struct scsi_device ncr5380_dev = {
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1995-04-21 06:47:35 +04:00
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NULL, /* Use default error handler. */
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NULL, /* have a queue, served by this (?) */
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NULL, /* have no async handler. */
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NULL, /* Use default "done" routine. */
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1993-11-29 03:32:22 +03:00
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};
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1993-09-29 09:08:37 +03:00
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1995-04-21 06:47:35 +04:00
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extern int matchbyname();
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static int ncrprobe();
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static void ncrattach();
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1994-01-30 04:08:50 +03:00
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1994-06-26 17:00:32 +04:00
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struct cfdriver ncrscsicd =
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1995-04-21 06:47:35 +04:00
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{NULL, "ncrscsi", ncrprobe, ncrattach,
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DV_DULL, sizeof(struct ncr5380_softc), NULL, 0};
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1994-01-30 04:08:50 +03:00
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1993-11-29 03:32:22 +03:00
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static int
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ncr_print(aux, name)
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1995-04-21 06:47:35 +04:00
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void *aux;
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char *name;
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1993-09-29 09:08:37 +03:00
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{
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1995-04-21 06:47:35 +04:00
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/* printf("%s: (sc_link = 0x%x)", name, (int) aux); return UNCONF; */
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1993-11-29 03:32:22 +03:00
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}
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1993-09-29 09:08:37 +03:00
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1994-01-30 04:08:50 +03:00
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static int
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1995-04-20 19:32:01 +04:00
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ncrprobe(parent, match, aux)
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1995-04-21 06:47:35 +04:00
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struct device *parent;
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void *match;
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void *aux;
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1993-11-29 03:32:22 +03:00
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{
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1995-04-21 06:47:35 +04:00
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static int probed = 0;
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struct ncr5380_softc *ncr5380;
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1993-09-29 09:08:37 +03:00
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1994-07-10 20:55:53 +04:00
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if (!mac68k_machine.scsi80) {
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1994-06-26 17:00:32 +04:00
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return 0;
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}
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1995-04-20 19:32:01 +04:00
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ncr5380 = (struct ncr5380_softc *) match;
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1993-09-29 09:08:37 +03:00
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1995-04-20 19:32:01 +04:00
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if (strcmp(*((char **) aux), ncr5380->sc_dev.dv_xname)) {
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1994-01-30 04:08:50 +03:00
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return 0;
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1993-11-29 03:32:22 +03:00
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}
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1994-06-26 17:00:32 +04:00
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if (!probed) {
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/*
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* Adjust values based on IOBase.
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*/
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1995-04-21 06:47:35 +04:00
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ncr = (volatile sci_regmap_t *) (IOBase + (u_int) ncr);
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sci_4byte_addr = (volatile long *)
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(IOBase + (u_int) sci_4byte_addr);
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sci_1byte_addr = (volatile u_char *)
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(IOBase + (u_int) sci_1byte_addr);
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1994-06-26 17:00:32 +04:00
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probed = 1;
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}
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1994-01-30 04:08:50 +03:00
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return 1;
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}
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static void
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ncrattach(parent, dev, aux)
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1995-04-21 06:47:35 +04:00
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struct device *parent, *dev;
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void *aux;
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1994-01-30 04:08:50 +03:00
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{
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1995-04-21 06:47:35 +04:00
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register volatile sci_padded_regmap_t *regs = ncr;
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int unit = dev->dv_unit;
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struct ncr5380_softc *ncr5380;
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int r;
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1994-01-30 04:08:50 +03:00
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1995-04-20 19:32:01 +04:00
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ncr5380 = (struct ncr5380_softc *) dev;
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1994-01-30 04:08:50 +03:00
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ncr5380->sc_link.scsibus = unit;
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1995-01-15 09:27:54 +03:00
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ncr5380->sc_link.adapter_target = 7;
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1993-11-29 03:32:22 +03:00
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ncr5380->sc_link.adapter = &ncr5380_switch;
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1994-06-26 17:00:32 +04:00
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ncr5380->sc_link.device = &ncr5380_dev;
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1995-02-01 16:50:42 +03:00
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ncr5380->sc_link.openings = 1;
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#ifdef SCSIDEBUG
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1995-04-21 06:47:35 +04:00
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ncr5380->sc_link.flags = SDEV_DB1 | SDEV_DB2 /* | SDEV_DB3 | SDEV_DB4 */ ;
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1995-02-01 16:50:42 +03:00
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#endif
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1993-11-29 03:32:22 +03:00
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1994-01-30 04:08:50 +03:00
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printf("\n");
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1993-11-29 03:32:22 +03:00
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1994-01-30 04:08:50 +03:00
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config_found(dev, &(ncr5380->sc_link), ncr_print);
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1993-09-29 09:08:37 +03:00
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}
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1995-04-21 06:47:35 +04:00
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#define MIN_PHYS 65536 /* BARF!!!! */
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1993-09-29 09:08:37 +03:00
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static void
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1995-04-21 06:47:35 +04:00
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ncr5380_minphys(struct buf * bp)
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1993-09-29 09:08:37 +03:00
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{
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if (bp->b_bcount > MIN_PHYS) {
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printf("Uh-oh... ncr5380_minphys setting bp->b_bcount = %x.\n", MIN_PHYS);
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bp->b_bcount = MIN_PHYS;
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}
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}
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#undef MIN_PHYS
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1994-01-30 04:08:50 +03:00
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static int
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1995-04-21 06:47:35 +04:00
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ncr5380_scsi_cmd(struct scsi_xfer * xs)
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1993-09-29 09:08:37 +03:00
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{
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1995-04-21 06:47:35 +04:00
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int flags, s, r;
|
1993-09-29 09:08:37 +03:00
|
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flags = xs->flags;
|
1995-04-21 06:47:35 +04:00
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if (xs->bp)
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flags |= (SCSI_NOSLEEP);
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if (flags & ITSDONE) {
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1993-09-29 09:08:37 +03:00
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printf("Already done?");
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xs->flags &= ~ITSDONE;
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}
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1995-04-21 06:47:35 +04:00
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if (!(flags & INUSE)) {
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1993-09-29 09:08:37 +03:00
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printf("Not in use?");
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xs->flags |= INUSE;
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}
|
1995-04-21 06:47:35 +04:00
|
|
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if (flags & SCSI_RESET) {
|
1993-09-29 09:08:37 +03:00
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printf("flags & SCSIRESET.\n");
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s = splbio();
|
1995-02-01 16:50:42 +03:00
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ncr5380_reset_target(xs->sc_link->scsibus,
|
1995-04-21 06:47:35 +04:00
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xs->sc_link->target);
|
1993-09-29 09:08:37 +03:00
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splx(s);
|
1995-04-21 06:47:35 +04:00
|
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return (COMPLETE);
|
1993-09-29 09:08:37 +03:00
|
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}
|
1995-04-21 06:47:35 +04:00
|
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xs->resid = 0;
|
1993-09-29 09:08:37 +03:00
|
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|
r = ncr5380_send_cmd(xs);
|
1993-11-29 03:32:22 +03:00
|
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xs->flags |= ITSDONE;
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|
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scsi_done(xs);
|
1995-02-01 16:50:42 +03:00
|
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|
#ifdef SCSIDEBUG
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|
printf("SCSI transfer done.\n");
|
1995-04-21 06:47:35 +04:00
|
|
|
#endif /* SCSIDEBUG */
|
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|
|
switch (r) {
|
|
|
|
case COMPLETE:
|
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|
|
case SUCCESSFULLY_QUEUED:
|
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|
|
r = SUCCESSFULLY_QUEUED;
|
|
|
|
if (xs->flags & SCSI_POLL)
|
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|
|
r = COMPLETE;
|
|
|
|
break;
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|
|
default:
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|
|
break;
|
1993-11-29 03:32:22 +03:00
|
|
|
}
|
1993-09-29 09:08:37 +03:00
|
|
|
return r;
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|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
ncr5380_show_scsi_cmd(struct scsi_xfer * xs)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
u_char *b = (u_char *) xs->cmd;
|
|
|
|
int i = 0;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
if (!(xs->flags & SCSI_RESET)) {
|
1993-09-29 09:08:37 +03:00
|
|
|
printf("ncr5380(%d:%d:%d)-",
|
1995-04-21 06:47:35 +04:00
|
|
|
xs->sc_link->scsibus, xs->sc_link->target, xs->sc_link->lun);
|
1993-09-29 09:08:37 +03:00
|
|
|
while (i < xs->cmdlen) {
|
1995-04-21 06:47:35 +04:00
|
|
|
if (i)
|
|
|
|
printf(",");
|
|
|
|
printf("%x", b[i++]);
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
printf("-\n");
|
|
|
|
} else {
|
|
|
|
printf("ncr5380(%d:%d:%d)-RESET-\n",
|
1995-04-21 06:47:35 +04:00
|
|
|
xs->sc_link->scsibus, xs->sc_link->target, xs->sc_link->lun);
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* Actual chip control.
|
|
|
|
*/
|
|
|
|
|
|
|
|
extern void
|
|
|
|
spinwait(int ms)
|
|
|
|
{
|
|
|
|
while (ms--)
|
1994-12-03 17:16:58 +03:00
|
|
|
delay(1000);
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
extern void
|
|
|
|
ncr5380_intr(int adapter)
|
|
|
|
{
|
|
|
|
register volatile sci_padded_regmap_t *regs = ncr;
|
|
|
|
|
|
|
|
SCI_CLR_INTR(regs);
|
1995-04-21 06:47:35 +04:00
|
|
|
regs->sci_mode = 0x00;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
extern int
|
1994-06-26 17:00:32 +04:00
|
|
|
ncr5380_irq_intr(void)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1993-11-29 03:32:22 +03:00
|
|
|
register volatile sci_padded_regmap_t *regs = ncr;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1993-11-29 03:32:22 +03:00
|
|
|
/* if (regs->sci_csr != SCI_CSR_PHASE_MATCH)
|
|
|
|
printf("scsi_irq_intr called (not just phase match -- "
|
|
|
|
"csr = 0x%x, bus_csr = 0x%x).\n",
|
|
|
|
regs->sci_csr, regs->sci_bus_csr);
|
|
|
|
ncr5380_intr(0); */
|
1993-09-29 09:08:37 +03:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
extern int
|
1994-06-26 17:00:32 +04:00
|
|
|
ncr5380_drq_intr(void)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1993-11-29 03:32:22 +03:00
|
|
|
/* printf("scsi_drq_intr called.\n"); */
|
|
|
|
/* ncr5380_intr(0); */
|
1993-09-29 09:08:37 +03:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
ncr5380_reset_target(int adapter, int target)
|
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile sci_padded_regmap_t *regs = ncr;
|
|
|
|
int dummy;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
regs->sci_icmd = SCI_ICMD_TEST;
|
|
|
|
regs->sci_icmd = SCI_ICMD_TEST | SCI_ICMD_RST;
|
1995-04-21 06:47:35 +04:00
|
|
|
spinwait(250); /* 250 ms */
|
1993-09-29 09:08:37 +03:00
|
|
|
regs->sci_icmd = 0;
|
|
|
|
|
|
|
|
regs->sci_mode = 0;
|
|
|
|
regs->sci_tcmd = SCI_PHASE_DISC;
|
|
|
|
regs->sci_sel_enb = 0;
|
|
|
|
|
|
|
|
SCI_CLR_INTR(regs);
|
|
|
|
SCI_CLR_INTR(regs);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
ncr5380_poll(int adapter, int timeout)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
ncr5380_send_cmd(struct scsi_xfer * xs)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
int s;
|
|
|
|
int sense;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-02-01 16:50:42 +03:00
|
|
|
#ifdef SCSIDEBUG
|
|
|
|
ncr5380_show_scsi_cmd(xs);
|
|
|
|
#endif
|
1993-09-29 09:08:37 +03:00
|
|
|
s = splbio();
|
1995-04-21 06:47:35 +04:00
|
|
|
sense = scsi_gen(xs->sc_link->scsibus, xs->sc_link->target,
|
|
|
|
xs->sc_link->lun, xs->cmd, xs->cmdlen,
|
|
|
|
xs->data, xs->datalen);
|
1993-09-29 09:08:37 +03:00
|
|
|
splx(s);
|
|
|
|
if (sense) {
|
|
|
|
switch (sense) {
|
1995-04-21 06:47:35 +04:00
|
|
|
case 0x02: /* Check condition */
|
1993-09-29 09:08:37 +03:00
|
|
|
/* printf("check cond. target %d.\n", xs->targ);*/
|
1995-04-21 06:47:35 +04:00
|
|
|
s = splbio();
|
|
|
|
scsi_group0(xs->sc_link->scsibus,
|
|
|
|
xs->sc_link->target,
|
|
|
|
xs->sc_link->lun,
|
|
|
|
0x3, 0x0,
|
|
|
|
sizeof(struct scsi_sense_data),
|
|
|
|
0, (caddr_t) & (xs->sense),
|
|
|
|
sizeof(struct scsi_sense_data));
|
|
|
|
splx(s);
|
|
|
|
xs->error = XS_SENSE;
|
|
|
|
return COMPLETE;
|
|
|
|
case 0x08: /* Busy */
|
|
|
|
xs->error = XS_BUSY;
|
|
|
|
return COMPLETE;
|
|
|
|
default:
|
|
|
|
xs->error = XS_DRIVER_STUFFUP;
|
|
|
|
return COMPLETE;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
xs->error = XS_NOERROR;
|
|
|
|
return (COMPLETE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
select_target(register volatile sci_padded_regmap_t * regs,
|
|
|
|
u_char myid, u_char tid, int with_atn)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register u_char bid, icmd;
|
|
|
|
int ret = SCSI_RET_RETRY;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
if ((regs->sci_bus_csr & (SCI_BUS_BSY | SCI_BUS_SEL)) &&
|
|
|
|
(regs->sci_bus_csr & (SCI_BUS_BSY | SCI_BUS_SEL)) &&
|
|
|
|
(regs->sci_bus_csr & (SCI_BUS_BSY | SCI_BUS_SEL)))
|
1993-09-29 09:08:37 +03:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* for our purposes.. */
|
|
|
|
myid = 1 << myid;
|
|
|
|
tid = 1 << tid;
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
regs->sci_sel_enb = 0; /* myid; we don't want any interrupts. */
|
1995-02-01 16:50:42 +03:00
|
|
|
regs->sci_tcmd = 0; /* Get into a harmless state. */
|
|
|
|
regs->sci_mode = 0; /* Get into a harmless state. */
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
regs->sci_odata = myid;
|
|
|
|
regs->sci_mode = SCI_MODE_ARB;
|
|
|
|
/* regs->sci_mode |= SCI_MODE_ARB; */
|
|
|
|
/* AIP might not set if BSY went true after we checked */
|
|
|
|
for (bid = 0; bid < 20; bid++) /* 20usec circa */
|
|
|
|
if (regs->sci_icmd & SCI_ICMD_AIP)
|
|
|
|
break;
|
|
|
|
if ((regs->sci_icmd & SCI_ICMD_AIP) == 0) {
|
|
|
|
goto lost;
|
|
|
|
}
|
1995-04-21 06:47:35 +04:00
|
|
|
delay(3); /* 2.4us arb delay */
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
if (regs->sci_icmd & SCI_ICMD_LST) {
|
|
|
|
goto lost;
|
|
|
|
}
|
|
|
|
regs->sci_mode &= ~SCI_MODE_PAR_CHK;
|
|
|
|
bid = regs->sci_data;
|
|
|
|
|
|
|
|
if ((bid & ~myid) > myid) {
|
|
|
|
goto lost;
|
|
|
|
}
|
|
|
|
if (regs->sci_icmd & SCI_ICMD_LST) {
|
|
|
|
goto lost;
|
|
|
|
}
|
1995-04-21 06:47:35 +04:00
|
|
|
/* Won arbitration, enter selection phase now */
|
|
|
|
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF | SCI_ICMD_TEST);
|
|
|
|
icmd |= (with_atn ? (SCI_ICMD_SEL | SCI_ICMD_ATN) : SCI_ICMD_SEL);
|
1993-09-29 09:08:37 +03:00
|
|
|
icmd |= SCI_ICMD_BSY;
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
|
|
|
|
if (regs->sci_icmd & SCI_ICMD_LST) {
|
|
|
|
goto nosel;
|
|
|
|
}
|
|
|
|
/* XXX a target that violates specs might still drive the bus XXX */
|
|
|
|
/* XXX should put our id out, and after the delay check nothi XXX */
|
|
|
|
/* XXX ng else is out there. XXX */
|
|
|
|
|
1994-12-03 17:16:58 +03:00
|
|
|
delay(1);
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
regs->sci_tcmd = 0;
|
|
|
|
regs->sci_odata = myid | tid;
|
|
|
|
regs->sci_sel_enb = 0;
|
|
|
|
|
|
|
|
/* regs->sci_mode &= ~SCI_MODE_ARB; 2 deskew delays, too */
|
1995-04-21 06:47:35 +04:00
|
|
|
regs->sci_mode = 0; /* 2 deskew delays, too */
|
|
|
|
|
1993-09-29 09:08:37 +03:00
|
|
|
icmd |= SCI_ICMD_DATA;
|
|
|
|
icmd &= ~(SCI_ICMD_BSY);
|
|
|
|
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
|
|
|
|
/* bus settle delay, 400ns */
|
1995-04-21 06:47:35 +04:00
|
|
|
delay(1); /* 1us > 400ns ;-) */
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
/* regs->sci_mode |= SCI_MODE_PAR_CHK; */
|
|
|
|
|
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register int timeo = 2500; /* 250 msecs in 100 usecs
|
|
|
|
* chunks */
|
1993-09-29 09:08:37 +03:00
|
|
|
while ((regs->sci_bus_csr & SCI_BUS_BSY) == 0) {
|
|
|
|
if (--timeo > 0) {
|
|
|
|
delay(100);
|
|
|
|
} else {
|
|
|
|
goto nodev;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
icmd &= ~(SCI_ICMD_DATA | SCI_ICMD_SEL);
|
1993-09-29 09:08:37 +03:00
|
|
|
regs->sci_icmd = icmd;
|
1995-04-21 06:47:35 +04:00
|
|
|
/* regs->sci_sel_enb = myid;*//* looks like we should NOT have it */
|
1993-09-29 09:08:37 +03:00
|
|
|
return SCSI_RET_SUCCESS;
|
|
|
|
nodev:
|
|
|
|
ret = SCSI_RET_DEVICE_DOWN;
|
|
|
|
regs->sci_sel_enb = myid;
|
|
|
|
nosel:
|
1995-04-21 06:47:35 +04:00
|
|
|
icmd &= ~(SCI_ICMD_DATA | SCI_ICMD_SEL | SCI_ICMD_ATN);
|
1993-09-29 09:08:37 +03:00
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
lost:
|
|
|
|
regs->sci_mode = 0;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
1994-06-26 17:00:32 +04:00
|
|
|
static int
|
1993-09-29 09:08:37 +03:00
|
|
|
sci_data_out(regs, phase, count, data)
|
1995-04-21 06:47:35 +04:00
|
|
|
register sci_padded_regmap_t *regs;
|
|
|
|
unsigned char *data;
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register unsigned char icmd;
|
|
|
|
register int cnt = 0;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
/* ..checks.. */
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF | SCI_ICMD_TEST);
|
1993-09-29 09:08:37 +03:00
|
|
|
loop:
|
|
|
|
if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
|
|
|
|
return cnt;
|
|
|
|
|
|
|
|
WAIT_FOR_REQ(regs);
|
|
|
|
icmd |= SCI_ICMD_DATA;
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
regs->sci_odata = *data++;
|
|
|
|
icmd |= SCI_ICMD_ACK;
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
icmd &= ~(SCI_ICMD_DATA | SCI_ICMD_ACK);
|
1993-09-29 09:08:37 +03:00
|
|
|
WAIT_FOR_NOT_REQ(regs);
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
++cnt;
|
|
|
|
if (--count > 0)
|
|
|
|
goto loop;
|
|
|
|
scsi_timeout_error:
|
|
|
|
return cnt;
|
|
|
|
}
|
|
|
|
|
1994-06-26 17:00:32 +04:00
|
|
|
static int
|
1993-09-29 09:08:37 +03:00
|
|
|
sci_data_in(regs, phase, count, data)
|
1995-04-21 06:47:35 +04:00
|
|
|
register sci_padded_regmap_t *regs;
|
|
|
|
unsigned char *data;
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register unsigned char icmd;
|
|
|
|
register int cnt = 0;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
/* ..checks.. */
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
icmd = regs->sci_icmd & ~(SCI_ICMD_DIFF | SCI_ICMD_TEST);
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
loop:
|
|
|
|
if (SCI_CUR_PHASE(regs->sci_bus_csr) != phase)
|
|
|
|
return cnt;
|
|
|
|
|
|
|
|
WAIT_FOR_REQ(regs);
|
|
|
|
*data++ = regs->sci_data;
|
|
|
|
icmd |= SCI_ICMD_ACK;
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
|
|
|
|
icmd &= ~SCI_ICMD_ACK;
|
|
|
|
WAIT_FOR_NOT_REQ(regs);
|
|
|
|
regs->sci_icmd = icmd;
|
|
|
|
++cnt;
|
|
|
|
if (--count > 0)
|
|
|
|
goto loop;
|
|
|
|
|
|
|
|
scsi_timeout_error:
|
|
|
|
return cnt;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
command_transfer(register volatile sci_padded_regmap_t * regs,
|
|
|
|
int maxlen, u_char * data, u_char * status, u_char * msg)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
int xfer = 0, phase;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
/* printf("command_transfer called for 0x%x.\n", *data); */
|
|
|
|
|
|
|
|
regs->sci_icmd = 0;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
|
|
|
|
WAIT_FOR_REQ(regs);
|
|
|
|
|
|
|
|
phase = SCI_CUR_PHASE(regs->sci_bus_csr);
|
|
|
|
|
|
|
|
switch (phase) {
|
1995-04-21 06:47:35 +04:00
|
|
|
case SCSI_PHASE_CMD:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_CMD);
|
|
|
|
xfer += sci_data_out(regs, SCSI_PHASE_CMD,
|
|
|
|
maxlen, data);
|
|
|
|
return xfer;
|
|
|
|
case SCSI_PHASE_DATA_IN:
|
|
|
|
printf("Data in phase in command_transfer?\n");
|
|
|
|
return 0;
|
|
|
|
case SCSI_PHASE_DATA_OUT:
|
|
|
|
printf("Data out phase in command_transfer?\n");
|
|
|
|
return 0;
|
|
|
|
case SCSI_PHASE_STATUS:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_STATUS);
|
|
|
|
printf("status in command_transfer.\n");
|
|
|
|
sci_data_in(regs, SCSI_PHASE_STATUS,
|
|
|
|
1, status);
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_MESSAGE_IN:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_MESSAGE_IN);
|
|
|
|
printf("msgin in command_transfer.\n");
|
|
|
|
sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
|
|
|
|
1, msg);
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_MESSAGE_OUT:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_MESSAGE_OUT);
|
|
|
|
sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
|
|
|
|
1, msg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("Unexpected phase 0x%x in "
|
|
|
|
"command_transfer().\n", phase);
|
|
|
|
scsi_timeout_error:
|
|
|
|
return xfer;
|
|
|
|
break;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
data_transfer(register volatile sci_padded_regmap_t * regs,
|
|
|
|
int maxlen, u_char * data, u_char * status, u_char * msg)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
int retlen = 0, xfer, phase;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
regs->sci_icmd = 0;
|
|
|
|
|
|
|
|
*status = 0;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
|
|
|
|
WAIT_FOR_REQ(regs);
|
|
|
|
|
|
|
|
phase = SCI_CUR_PHASE(regs->sci_bus_csr);
|
|
|
|
|
|
|
|
switch (phase) {
|
1995-04-21 06:47:35 +04:00
|
|
|
case SCSI_PHASE_CMD:
|
|
|
|
printf("Command phase in data_transfer().\n");
|
|
|
|
return retlen;
|
|
|
|
case SCSI_PHASE_DATA_IN:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_DATA_IN);
|
1993-09-29 09:08:37 +03:00
|
|
|
#if PSEUDO_DMA
|
1995-04-21 06:47:35 +04:00
|
|
|
xfer = sci_pdma_in(regs, SCSI_PHASE_DATA_IN,
|
|
|
|
maxlen, data);
|
1993-09-29 09:08:37 +03:00
|
|
|
#else
|
1995-04-21 06:47:35 +04:00
|
|
|
xfer = sci_data_in(regs, SCSI_PHASE_DATA_IN,
|
|
|
|
maxlen, data);
|
1993-09-29 09:08:37 +03:00
|
|
|
#endif
|
1995-04-21 06:47:35 +04:00
|
|
|
retlen += xfer;
|
|
|
|
maxlen -= xfer;
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_DATA_OUT:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_DATA_OUT);
|
1993-09-29 09:08:37 +03:00
|
|
|
#if PSEUDO_DMA
|
1995-04-21 06:47:35 +04:00
|
|
|
xfer = sci_pdma_out(regs, SCSI_PHASE_DATA_OUT,
|
|
|
|
maxlen, data);
|
1993-09-29 09:08:37 +03:00
|
|
|
#else
|
1995-04-21 06:47:35 +04:00
|
|
|
xfer = sci_data_out(regs, SCSI_PHASE_DATA_OUT,
|
|
|
|
maxlen, data);
|
1993-09-29 09:08:37 +03:00
|
|
|
#endif
|
1995-04-21 06:47:35 +04:00
|
|
|
retlen += xfer;
|
|
|
|
maxlen -= xfer;
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_STATUS:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_STATUS);
|
|
|
|
sci_data_in(regs, SCSI_PHASE_STATUS,
|
|
|
|
1, status);
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_MESSAGE_IN:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_MESSAGE_IN);
|
|
|
|
sci_data_in(regs, SCSI_PHASE_MESSAGE_IN,
|
|
|
|
1, msg);
|
|
|
|
if (*msg == 0) {
|
1993-09-29 09:08:37 +03:00
|
|
|
return retlen;
|
1995-04-21 06:47:35 +04:00
|
|
|
} else {
|
|
|
|
printf("message 0x%x in "
|
|
|
|
"data_transfer.\n", *msg);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case SCSI_PHASE_MESSAGE_OUT:
|
|
|
|
SCI_ACK(regs, SCSI_PHASE_MESSAGE_OUT);
|
|
|
|
sci_data_out(regs, SCSI_PHASE_MESSAGE_OUT,
|
|
|
|
1, msg);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("Unexpected phase 0x%x in "
|
|
|
|
"data_transfer().\n", phase);
|
|
|
|
scsi_timeout_error:
|
|
|
|
return retlen;
|
|
|
|
break;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
scsi_request(register volatile sci_padded_regmap_t * regs,
|
|
|
|
int target, int lun, u_char * cmd, int cmdlen,
|
|
|
|
char *databuf, int datalen, int *sent, int *ret)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
|
|
|
/* Returns 0 on success, -1 on internal error, or the status byte */
|
1995-04-21 06:47:35 +04:00
|
|
|
int cmd_bytes_sent, r;
|
|
|
|
u_char stat, msg, c;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
*sent = 0;
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
if ((r = select_target(regs, 7, target, 1)) != SCSI_RET_SUCCESS) {
|
1993-09-29 09:08:37 +03:00
|
|
|
*ret = r;
|
|
|
|
SCI_CLR_INTR(regs);
|
|
|
|
switch (r) {
|
|
|
|
case SCSI_RET_RETRY:
|
|
|
|
return 0x08;
|
|
|
|
default:
|
|
|
|
printf("select_target(target %d, lun %d) failed(%d).\n",
|
1995-04-21 06:47:35 +04:00
|
|
|
target, lun, r);
|
1993-09-29 09:08:37 +03:00
|
|
|
case SCSI_RET_DEVICE_DOWN:
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
c = 0x80 | lun;
|
|
|
|
|
|
|
|
if ((cmd_bytes_sent = command_transfer(regs, cmdlen,
|
1995-04-21 06:47:35 +04:00
|
|
|
(u_char *) cmd, &stat, &c))
|
|
|
|
!= cmdlen) {
|
1993-09-29 09:08:37 +03:00
|
|
|
SCI_CLR_INTR(regs);
|
|
|
|
*ret = SCSI_RET_COMMAND_FAIL;
|
|
|
|
printf("Data underrun sending CCB (%d bytes of %d, sent).\n",
|
1995-04-21 06:47:35 +04:00
|
|
|
cmd_bytes_sent, cmdlen);
|
1993-09-29 09:08:37 +03:00
|
|
|
return -1;
|
|
|
|
}
|
1995-04-21 06:47:35 +04:00
|
|
|
*sent = data_transfer(regs, datalen, (u_char *) databuf,
|
|
|
|
&stat, &msg);
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
*ret = 0;
|
|
|
|
|
|
|
|
return stat;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1995-04-21 06:47:35 +04:00
|
|
|
scsi_gen(int adapter, int id, int lun, struct scsi_generic * cmd,
|
|
|
|
int cmdlen, void *databuf, int datalen)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile sci_padded_regmap_t *regs = ncr;
|
|
|
|
int i, j, sent, ret;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
cmd->bytes[0] = ((u_char) lun << 5);
|
1993-12-15 06:17:54 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
i = scsi_request(regs, id, lun, (u_char *) cmd, cmdlen,
|
|
|
|
databuf, datalen, &sent, &ret);
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
return i;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
1993-12-15 06:17:54 +03:00
|
|
|
scsi_group0(int adapter, int id, int lun, int opcode, int addr, int len,
|
1995-04-21 06:47:35 +04:00
|
|
|
int flags, caddr_t databuf, int datalen)
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile sci_padded_regmap_t *regs = ncr;
|
|
|
|
unsigned char cmd[6];
|
|
|
|
int i, j, sent, ret;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
cmd[0] = opcode; /* Operation code */
|
|
|
|
cmd[1] = (lun << 5) | ((addr >> 16) & 0x1F); /* Lun & MSB of addr */
|
|
|
|
cmd[2] = (addr >> 8) & 0xFF; /* addr */
|
|
|
|
cmd[3] = addr & 0xFF; /* LSB of addr */
|
|
|
|
cmd[4] = len; /* Allocation length */
|
|
|
|
cmd[5] = flags; /* Link/Flag */
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
i = scsi_request(regs, id, lun, cmd, 6, databuf, datalen, &sent, &ret);
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
return i;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
/* pseudo-dma action */
|
|
|
|
|
|
|
|
#if PSEUDO_DMA
|
|
|
|
|
|
|
|
#define TIMEOUT 1000000
|
|
|
|
#define READY(poll) \
|
|
|
|
i = TIMEOUT; \
|
|
|
|
while ((regs->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) \
|
|
|
|
!=(SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) \
|
|
|
|
if ( !(regs->sci_csr & SCI_CSR_PHASE_MATCH) \
|
|
|
|
|| !(regs->sci_bus_csr & SCI_BUS_BSY) \
|
|
|
|
|| (i-- < 0) ) { \
|
|
|
|
printf("scsi.c: timeout counter = %d, len = %d count=%d (count-len %d).\n", \
|
|
|
|
i, len,count,count-len); \
|
|
|
|
printf("pdebug = %d, 1=out, 2=in",pdebug); \
|
|
|
|
/*dump_regs();*/ \
|
|
|
|
if (poll && !(regs->sci_csr & SCI_CSR_PHASE_MATCH)) { \
|
|
|
|
regs->sci_icmd &= ~SCI_ICMD_DATA; \
|
|
|
|
len--; \
|
|
|
|
} else { \
|
|
|
|
regs->sci_mode &= ~SCI_MODE_DMA; \
|
|
|
|
} \
|
|
|
|
return count-len; \
|
|
|
|
}
|
|
|
|
|
|
|
|
#define W1 *byte_data = *data++
|
|
|
|
#define W4 *long_data = *((long*)data)++
|
|
|
|
|
|
|
|
sci_pdma_out(regs, phase, count, data)
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile sci_padded_regmap_t *regs;
|
|
|
|
int phase;
|
|
|
|
int count;
|
|
|
|
u_char *data;
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile long *long_data = sci_4byte_addr;
|
|
|
|
register volatile u_char *byte_data = sci_1byte_addr;
|
|
|
|
register int len = count, i;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
pdebug = 1;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
if (count < 128)
|
|
|
|
return sci_data_out(regs, phase, count, data);
|
|
|
|
|
|
|
|
WAIT_FOR_BSY(regs);
|
|
|
|
regs->sci_mode |= SCI_MODE_DMA;
|
|
|
|
regs->sci_icmd |= SCI_ICMD_DATA;
|
|
|
|
regs->sci_dma_send = 0;
|
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
while (len >= 64) {
|
|
|
|
READY(1);
|
|
|
|
W1;
|
|
|
|
READY(1);
|
|
|
|
W1;
|
|
|
|
READY(1);
|
|
|
|
W1;
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(1);
|
1995-04-21 06:47:35 +04:00
|
|
|
W1;
|
|
|
|
READY(1);
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
|
|
|
W4;
|
1993-09-29 09:08:37 +03:00
|
|
|
len -= 64;
|
|
|
|
}
|
|
|
|
while (len) {
|
|
|
|
READY(1);
|
|
|
|
W1;
|
|
|
|
len--;
|
|
|
|
}
|
|
|
|
i = TIMEOUT;
|
1995-04-21 06:47:35 +04:00
|
|
|
while (((regs->sci_csr & (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))
|
1993-09-29 09:08:37 +03:00
|
|
|
== SCI_CSR_PHASE_MATCH) && --i);
|
|
|
|
if (!i)
|
|
|
|
printf("scsi.c:%d: timeout waiting for SCI_CSR_DREQ.\n", __LINE__);
|
|
|
|
*byte_data = 0;
|
|
|
|
scsi_timeout_error:
|
|
|
|
regs->sci_mode &= ~SCI_MODE_DMA;
|
1995-04-21 06:47:35 +04:00
|
|
|
return count - len;
|
1993-09-29 09:08:37 +03:00
|
|
|
}
|
|
|
|
#undef W1
|
|
|
|
#undef W4
|
|
|
|
|
|
|
|
#define R4 *((long *)data)++ = *long_data
|
|
|
|
#define R1 *data++ = *byte_data
|
|
|
|
|
|
|
|
sci_pdma_in(regs, phase, count, data)
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile sci_padded_regmap_t *regs;
|
|
|
|
int phase;
|
|
|
|
int count;
|
|
|
|
u_char *data;
|
1993-09-29 09:08:37 +03:00
|
|
|
{
|
1995-04-21 06:47:35 +04:00
|
|
|
register volatile long *long_data = sci_4byte_addr;
|
|
|
|
register volatile u_char *byte_data = sci_1byte_addr;
|
|
|
|
register int len = count, i;
|
1993-09-29 09:08:37 +03:00
|
|
|
|
1995-04-21 06:47:35 +04:00
|
|
|
pdebug = 2;
|
1993-09-29 09:08:37 +03:00
|
|
|
if (count < 128)
|
|
|
|
return sci_data_in(regs, phase, count, data);
|
|
|
|
|
1993-11-29 03:32:22 +03:00
|
|
|
/* printf("Called sci_pdma_in(0x%x, 0x%x, %d, 0x%x.\n", regs, phase, count, data); */
|
1993-09-29 09:08:37 +03:00
|
|
|
|
|
|
|
WAIT_FOR_BSY(regs);
|
|
|
|
regs->sci_mode |= SCI_MODE_DMA;
|
|
|
|
regs->sci_icmd |= SCI_ICMD_DATA;
|
|
|
|
regs->sci_irecv = 0;
|
|
|
|
|
|
|
|
while (len >= 1024) {
|
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 128 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 256 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 384 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 512 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 640 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 768 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 896 */
|
1993-09-29 09:08:37 +03:00
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 1024 */
|
1993-09-29 09:08:37 +03:00
|
|
|
len -= 1024;
|
|
|
|
}
|
|
|
|
while (len >= 128) {
|
|
|
|
READY(0);
|
1995-04-21 06:47:35 +04:00
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4;
|
|
|
|
R4; /* 128 */
|
1993-09-29 09:08:37 +03:00
|
|
|
len -= 128;
|
|
|
|
}
|
|
|
|
while (len) {
|
|
|
|
READY(0);
|
|
|
|
R1;
|
|
|
|
len--;
|
|
|
|
}
|
|
|
|
scsi_timeout_error:
|
|
|
|
regs->sci_mode &= ~SCI_MODE_DMA;
|
|
|
|
return count - len;
|
|
|
|
}
|
|
|
|
#undef R4
|
|
|
|
#undef R1
|
|
|
|
#endif
|