NetBSD/sys/lib/libkern/arch/mips/memcpy.S

/*	$NetBSD: memcpy.S,v 1.1 1998/09/11 16:46:34 jonathan Exp $	*/

#include <mips/asm.h>
#include <machine/endian.h>

	.data
	.globl	__no_memcpy
__no_memcpy:	.word 0
Changes to sys/arch/mips from ARC port, from Noriyuki Soda <soda@sra.co.jp>. Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff. 1998-09-11 20:46:31 +04:00			`/* $NetBSD: memcpy.S,v 1.1 1998/09/11 16:46:34 jonathan Exp $ */`

			`#include <mips/asm.h>`
			`#include <machine/endian.h>`

			`.data`
			`.globl __no_memcpy`
			`__no_memcpy: .word 0`