130 lines
4.4 KiB
C
130 lines
4.4 KiB
C
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/* $NetBSD: mb89352reg.h,v 1.1.1.1 1996/05/05 12:17:03 oki Exp $ */
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/*
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* Copyright (c) 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)scsireg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* FUJITSU MB89352A SCSI Protocol Controler Hardware Description.
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*/
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struct mb89352 {
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u_char p32, scsi_bdid;
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u_char p34, scsi_sctl;
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#define SCTL_DISABLE 0x80
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#define SCTL_CTRLRST 0x40
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#define SCTL_DIAG 0x20
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#define SCTL_ABRT_ENAB 0x10
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#define SCTL_PARITY_ENAB 0x08
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#define SCTL_SEL_ENAB 0x04
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#define SCTL_RESEL_ENAB 0x02
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#define SCTL_INTR_ENAB 0x01
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u_char p36, scsi_scmd;
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#define SCMD_RST 0x10
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#define SCMD_ICPT_XFR 0x08
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#define SCMD_PROG_XFR 0x04
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#define SCMD_PAD 0x01 /* if initiator */
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#define SCMD_PERR_STOP 0x01 /* if target */
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/* command codes */
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#define SCMD_BUS_REL 0x00
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#define SCMD_SELECT 0x20
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#define SCMD_RST_ATN 0x40
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#define SCMD_SET_ATN 0x60
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#define SCMD_XFR 0x80
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#define SCMD_XFR_PAUSE 0xa0
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#define SCMD_RST_ACK 0xc0
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#define SCMD_SET_ACK 0xe0
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u_char p38, scsi_tmod;
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#define TMOD_SYNC 0x80
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u_char p40, scsi_ints;
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#define INTS_SEL 0x80
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#define INTS_RESEL 0x40
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#define INTS_DISCON 0x20
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#define INTS_CMD_DONE 0x10
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#define INTS_SRV_REQ 0x08
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#define INTS_TIMEOUT 0x04
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#define INTS_HARD_ERR 0x02
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#define INTS_RST 0x01
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u_char p42, scsi_psns;
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#define PSNS_REQ 0x80
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#define PSNS_ACK 0x40
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#define PSNS_ATN 0x20
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#define PSNS_SEL 0x10
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#define PSNS_BSY 0x08
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u_char p44, scsi_ssts;
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#define SSTS_INITIATOR 0x80
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#define SSTS_TARGET 0x40
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#define SSTS_BUSY 0x20
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#define SSTS_XFR 0x10
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#define SSTS_ACTIVE (SSTS_INITIATOR|SSTS_XFR)
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#define SSTS_RST 0x08
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#define SSTS_TCZERO 0x04
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#define SSTS_DREG_FULL 0x02
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#define SSTS_DREG_EMPTY 0x01
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u_char p46, scsi_serr;
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#define SERR_SCSI_PAR 0x80
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#define SERR_SPC_PAR 0x40
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#define SERR_TC_PAR 0x08
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#define SERR_PHASE_ERR 0x04
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#define SERR_SHORT_XFR 0x02
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#define SERR_OFFSET 0x01
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u_char p48, scsi_pctl;
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#define PCTL_BFINT_ENAB 0x80
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u_char p50, scsi_mbc;
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u_char p52, scsi_dreg;
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u_char p54, scsi_temp;
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u_char p56, scsi_tch;
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u_char p58, scsi_tcm;
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u_char p60, scsi_tcl;
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u_char p62, scsi_exbf;
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};
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/* psns/pctl phase lines as bits */
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#define PHASE_MSG 0x04
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#define PHASE_CD 0x02 /* =1 if 'command' */
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#define PHASE_IO 0x01 /* =1 if data inbound */
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/* Phase lines as values */
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#define PHASE 0x07 /* mask for psns/pctl phase */
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#define DATA_OUT_PHASE 0x00
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#define DATA_IN_PHASE 0x01
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#define CMD_PHASE 0x02
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#define STATUS_PHASE 0x03
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#define BUS_FREE_PHASE 0x04
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */
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#define MESG_OUT_PHASE 0x06
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#define MESG_IN_PHASE 0x07
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