60 lines
2.1 KiB
C
60 lines
2.1 KiB
C
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/* $NetBSD: txcsbusvar.h,v 1.1 1999/11/20 19:56:40 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Chip Select bus attach arguments.
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*/
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struct csbus_attach_args {
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char *cba_busname;
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tx_chipset_tag_t cba_tc;
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};
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/*
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* Information for Chip Select CS[0:3], MCS[0:3], CARD[1:2]
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*/
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struct cs_handle {
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int cs; /* Chip Select. see tx39biuvar.h */
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u_int32_t csbase; /* base offset from CS start addr */
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u_int32_t cssize; /* map size */
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int cswidth; /* CS bus-width */
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bus_space_tag_t cstag; /* bus_space tag for this CS */
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};
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/*
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* Chip Select attach arguments.
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*/
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struct cs_attach_args {
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tx_chipset_tag_t ca_tc;
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struct cs_handle ca_csreg; /* Register space */
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struct cs_handle ca_csio; /* I/O space */
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struct cs_handle ca_csmem; /* Memory space */
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int ca_irq1; /* Interrupt request */
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int ca_irq2; /* 2nd interrupt request */
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int ca_irq3; /* 3rd interrupt request */
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};
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