59 lines
2.8 KiB
C
59 lines
2.8 KiB
C
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/* $NetBSD: amdpm_smbusreg.h,v 1.1 2006/02/19 02:24:20 tls Exp $ */
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/*
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* Copyright (c) 2005 Anil Gopinath (anil_public@yahoo.com)
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* driver for SMBUS 1.0 host controller found in the
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* AMD-8111 HyperTransport I/O Hub
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*/
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#ifndef _DEV_PCI_AMDPMSMBUSREG_H_
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#define _DEV_PCI_AMDPMSMBUSREG_H_
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#define AMDPM_8111_SMBUS_STAT 0xE0 /* SMBus 1.x global status register */
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#define AMDPM_8111_SMBUS_CTRL 0xE2 /* SMBus 1.x global control register */
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#define AMDPM_8111_SMBUS_HOSTADDR 0xE4 /* SMBus 1.x Host address register */
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#define AMDPM_8111_SMBUS_HOSTDATA 0xE6 /* SMBus 1.x Host data register */
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#define AMDPM_8111_SMBUS_HOSTCMD 0xE8 /* SMBus 1.x Host command field register */
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#define AMDPM_8111_SMBUS_GSR_SB 0x0009 /* GSR contents to send a byte */
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#define AMDPM_8111_SMBUS_GSR_RXB 0x0009 /* GSR contents to receive a byte */
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#define AMDPM_8111_SMBUS_GSR_RB 0x000A /* GSR contents to read a byte */
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#define AMDPM_8111_SMBUS_GSR_WB 0x000A /* GSR contents to write a byte */
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#define AMDPM_8111_GSR_CYCLE_DONE 0x0010 /* indicates cycle done successfuly */
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#define AMDPM_8111_SMBUS_READ 0x0001 /* smbus read cycle indicator */
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#define AMDPM_8111_SMBUS_RX 0x0001 /* smbus receive cycle indicator */
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#define AMDPM_8111_SMBUS_WRITE 0x0000 /* smbus write cycle indicator */
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#define AMDPM_8111_SMBUS_SEND 0x0000 /* smbus send cycle indicator */
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void amdpm_smbus_attach(struct amdpm_softc *sc);
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#endif
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