548 lines
16 KiB
C
548 lines
16 KiB
C
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/* $NetBSD: mq200debug.c,v 1.1 2001/03/25 13:06:53 takemura Exp $ */
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/*-
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* Copyright (c) 2001 TAKEMURA Shin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifdef _KERNEL
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#else
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#include <stdio.h>
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#endif
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#include <sys/types.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include "opt_mq200.h"
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#include "mq200var.h"
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#include "mq200reg.h"
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#include "mq200priv.h"
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#define ENABLE(b) ((b)?"enable":"disable")
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#ifdef MQ200_DEBUG
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char *mq200_clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
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void
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mq200_dump_pll(struct mq200_softc *sc)
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{
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int n, m;
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u_int32_t reg, pm00r;
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int clocks[4];
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int memclock, geclock;
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static char *clknames[] = { "BUS", "PLL1", "PLL2", "PLL3" };
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static char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
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static int fd_vals[] = { 10, 15, 25, 35, 45, 55, 65 };
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#define FIXEDFLOAT1000(a) (a)/1000, (a)%1000
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/* PM00R */
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pm00r = mq200_read(sc, MQ200_PMCR);
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geclock = (pm00r&MQ200_PMC_GE_CLK_MASK)>>MQ200_PMC_GE_CLK_SHIFT;
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/* MM01R */
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reg = mq200_read(sc, MQ200_MMR(1));
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memclock = (reg & MQ200_MM01_CLK_PLL2) ? 2 : 1;
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/* bus clock */
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clocks[0] = 0;
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/* PLL1 */
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reg = mq200_read(sc, MQ200_DCMISCR);
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m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
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n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) |
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((pm00r & MQ200_PMC_PLL1_N) << MQ200_PMC_PLL1_N_SHIFT));
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n <<= ((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT);
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printf(" PLL1:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
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FIXEDFLOAT1000(sc->sc_baseclock*m/n),
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reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
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clocks[1] = sc->sc_baseclock*m/n;
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/* PLL2 */
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if (pm00r & MQ200_PMC_PLL2_ENABLE) {
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reg = mq200_read(sc, MQ200_PLL2R);
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m = ((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1;
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n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) +1) <<
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((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
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clocks[2] = sc->sc_baseclock*m/n;
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printf(" PLL2:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
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FIXEDFLOAT1000(sc->sc_baseclock*m/n),
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reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
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} else {
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printf(" PLL2: disable\n");
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clocks[2] = 0;
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}
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/* PLL3 */
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if (pm00r & MQ200_PMC_PLL3_ENABLE) {
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reg = mq200_read(sc, MQ200_PLL3R);
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m = (((reg & MQ200_PLL_M_MASK) >> MQ200_PLL_M_SHIFT) + 1);
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n = ((((reg & MQ200_PLL_N_MASK) >> MQ200_PLL_N_SHIFT) + 1) <<
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((reg & MQ200_PLL_P_MASK) >> MQ200_PLL_P_SHIFT));
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clocks[3] = sc->sc_baseclock*m/n;
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printf(" PLL3:%3d.%03dMHz(0x%08x, %d.%03dMHzx%3d/%3d)\n",
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FIXEDFLOAT1000(sc->sc_baseclock*m/n),
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reg, FIXEDFLOAT1000(sc->sc_baseclock), m, n);
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} else {
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printf(" PLL3: disable\n");
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clocks[3] = 0;
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}
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printf(" MEM:%3d.%03dMHz(%s)\n",
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FIXEDFLOAT1000(clocks[memclock]),
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clknames[memclock]);
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printf(" GE:%3d.%03dMHz(%s)\n",
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FIXEDFLOAT1000(clocks[geclock]),
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clknames[geclock]);
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/* GC1 */
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reg = mq200_read(sc, MQ200_GCCR(MQ200_GC1));
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if (reg & MQ200_GCC_ENABLE) {
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int fd, sd, rc;
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rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
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fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
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sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
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printf(" GC1:%3d.%03dMHz(%s/%s/%d)",
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FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
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clknames[rc], fd_names[fd], sd);
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/* GC01R */
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reg = mq200_read(sc, MQ200_GC1CRTCR);
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if (reg&MQ200_GC1CRTC_DACEN)
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printf(", CRT");
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reg = mq200_read(sc, MQ200_FPCR);
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if ((reg & MQ200_FPC_ENABLE) && !(reg & MQ200_FPC_GC2))
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printf(", LCD");
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printf("\n");
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} else {
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printf(" GC1: disable\n");
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}
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/* GC2 */
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reg = mq200_read(sc, MQ200_GCCR(MQ200_GC2));
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if (reg & MQ200_GCC_ENABLE) {
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int fd, sd, rc;
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rc = (reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT;
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fd = (reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT;
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sd = (reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT;
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printf(" GC2:%3d.%03dMHz(%s/%s/%d)",
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FIXEDFLOAT1000(clocks[rc]*10/fd_vals[fd]/sd),
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clknames[rc], fd_names[fd], sd);
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reg = mq200_read(sc, MQ200_FPCR);
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if ((reg & MQ200_FPC_ENABLE) && (reg & MQ200_FPC_GC2))
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printf(", FP");
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printf("\n");
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} else {
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printf(" GC2: disable\n");
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}
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}
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struct {
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char *name;
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u_int32_t base;
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int start, end;
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} regs[] = {
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{ "GC", MQ200_GCR(0), 0x00, 0x13 },
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{ "GC", MQ200_GCR(0), 0x20, 0x33 },
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{ "FP", MQ200_FP, 0x00, 0x0f },
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{ "CC", MQ200_CC, 0x00, 0x01 },
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{ "PC", MQ200_PC, 0x00, 0x05 },
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{ "MM", MQ200_MM, 0x00, 0x04 },
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{ "DC", MQ200_DC, 0x00, 0x03 },
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{ "PM", MQ200_PM, 0x00, 0x03 },
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{ "PM", MQ200_PM, 0x06, 0x07 },
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{ "IN", MQ200_IN, 0x00, 0x03 },
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};
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char *
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mq200_regname(struct mq200_softc *sc, int offset, char *buf, int bufsize)
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{
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int i;
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for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
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if (regs[i].base + regs[i].start * 4 <= offset &&
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offset <= regs[i].base + regs[i].end * 4) {
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sprintf(buf, "%s%02XR", regs[i].name,
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(offset - regs[i].base) / 4);
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return (buf);
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}
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sprintf(buf, "OFFSET %02X", offset);
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return (buf);
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}
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void
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mq200_dump_all(struct mq200_softc *sc)
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{
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int i, j;
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for (i = 0; i < sizeof(regs)/sizeof(*regs); i++)
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for (j = regs[i].start; j <= regs[i].end; j++)
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printf("%s%02XR: %08x\n",
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regs[i].name, j,
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mq200_read(sc, regs[i].base + (j * 4)));
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}
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void
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mq200_write(struct mq200_softc *sc, int offset, u_int32_t data)
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{
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int i;
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char buf[32];
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for (i = 0; i < MQ200_I_MAX; i++) {
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if (sc->sc_regctxs[i].offset == offset)
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printf("mq200_write: WARNING: raw access %s\n",
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mq200_regname(sc, offset, buf, sizeof(buf)));
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}
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mq200_writex(sc, offset, data);
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}
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#if 0
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void
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mq200_dump_gc(struct mq200_softc *sc, int gc)
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{
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u_int32_t reg;
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char *depth_names[] = {
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"1bpp with CLUT",
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"2bpp with CLUT",
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"4bpp with CLUT",
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"8bpp with CLUT",
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"16bpp with CLUT",
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"24bpp with CLUT",
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"32bpp(RGB) with CLUT",
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"32bpp(BGR) with CLUT",
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"1bpp w/o CLUT",
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"2bpp w/o CLUT",
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"4bpp w/o CLUT",
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"8bpp w/o CLUT",
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"16bpp w/o CLUT",
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"24bpp w/o CLUT",
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"32bpp(RGB) w/o CLUT",
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"32bpp(BGR) w/o CLUT",
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};
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char *rc_names[] = { "BUS", "PLL1", "PLL2", "PLL3" };
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char *fd_names[] = { "1", "1.5", "2.5", "3.5", "4.5", "5.5", "6.5" };
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/*
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* GC00R Graphics Controller Control
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*/
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reg = mq200_read(sc, MQ200_GCCR(gc));
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printf("GC00R=0x%08x: ", reg);
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printf("%s %s%s%s%s%s\n",
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ENABLE(reg & MQ200_GCC_ENABLE),
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(reg & MQ200_GCC_HCRESET)?"HC_reset ":"",
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(reg & MQ200_GCC_VCRESET)?"VC_reset ":"",
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(reg & MQ200_GCC_HCEN)?"cursor_enable ":"",
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(reg & MQ200_GCC_TESTMODE0)?"test_mode0 ":"",
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(reg & MQ200_GCC_TESTMODE1)?"test_mode1 ":"");
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printf(" window: %s %s\n",
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ENABLE(reg & MQ200_GCC_WINEN),
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depth_names[(reg&MQ200_GCC_DEPTH_MASK)>>MQ200_GCC_DEPTH_SHIFT]);
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printf(" altwin: %s %s\n",
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ENABLE(reg & MQ200_GCC_ALTEN),
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depth_names[(reg&MQ200_GCC_ALTDEPTH_MASK)>>MQ200_GCC_ALTDEPTH_SHIFT]);
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printf(" clock: root_clock/first_div/second_div = %s/%s/%d\n",
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rc_names[(reg&MQ200_GCC_RCLK_MASK)>>MQ200_GCC_RCLK_SHIFT],
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fd_names[(reg&MQ200_GCC_MCLK_FD_MASK)>>MQ200_GCC_MCLK_FD_SHIFT],
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(reg&MQ200_GCC_MCLK_SD_MASK)>>MQ200_GCC_MCLK_SD_SHIFT);
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if (gc == 0) {
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/*
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* GC01R Graphics Controller CRT Control
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*/
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reg = mq200_read(sc, MQ200_GC1CRTCR);
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printf("GC01R=0x%08x:\n", reg);
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printf(" CRT DAC: %s\n",
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ENABLE(reg&MQ200_GC1CRTC_DACEN));
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printf(" power down mode: H-sync=");
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switch (reg & MQ200_GC1CRTC_HSYNC_PMMASK) {
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case MQ200_GC1CRTC_HSYNC_PMNORMAL:
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if (reg & MQ200_GC1CRTC_HSYNC_PMCLK)
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printf("PMCLK");
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else
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printf("LOW");
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break;
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case MQ200_GC1CRTC_HSYNC_PMLOW:
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printf("LOW");
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break;
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case MQ200_GC1CRTC_HSYNC_PMHIGH:
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printf("HIGH");
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break;
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default:
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printf("???");
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break;
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}
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printf(" V-sync=");
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switch (reg & MQ200_GC1CRTC_VSYNC_PMMASK) {
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case MQ200_GC1CRTC_VSYNC_PMNORMAL:
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if (reg & MQ200_GC1CRTC_VSYNC_PMCLK)
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printf("PMCLK");
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else
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printf("LOW");
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break;
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case MQ200_GC1CRTC_VSYNC_PMLOW:
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printf("LOW");
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break;
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case MQ200_GC1CRTC_VSYNC_PMHIGH:
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printf("HIGH");
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break;
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default:
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printf("???");
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break;
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}
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printf("\n");
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printf(" sync active: H=%s V=%s\n",
|
||
|
|
(reg & MQ200_GC1CRTC_HSYNC_ACTVLOW)?"low":"high",
|
||
|
|
(reg & MQ200_GC1CRTC_VSYNC_ACTVLOW)?"low":"high");
|
||
|
|
printf(" other: ");
|
||
|
|
if (reg & MQ200_GC1CRTC_SYNC_PEDESTAL_EN)
|
||
|
|
printf("Sync_pedestal ");
|
||
|
|
if (reg & MQ200_GC1CRTC_BLANK_PEDESTAL_EN)
|
||
|
|
printf("Blank_pedestal ");
|
||
|
|
if (reg & MQ200_GC1CRTC_COMPOSITE_SYNC_EN)
|
||
|
|
printf("Conposite_sync ");
|
||
|
|
if (reg & MQ200_GC1CRTC_VREF_EXTR)
|
||
|
|
printf("External_VREF ");
|
||
|
|
if (reg & MQ200_GC1CRTC_MONITOR_SENCE_EN) {
|
||
|
|
if (reg & MQ200_GC1CRTC_CONSTANT_OUTPUT_EN)
|
||
|
|
printf("Monitor_sence=%s%s%s/- ",
|
||
|
|
(reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",
|
||
|
|
(reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",
|
||
|
|
(reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G");
|
||
|
|
else
|
||
|
|
printf("Monitor_sence=%s%s%s/0x%02x ",
|
||
|
|
(reg & MQ200_GC1CRTC_BLUE_NOTLOADED)?"":"B",
|
||
|
|
(reg & MQ200_GC1CRTC_RED_NOTLOADED)?"":"R",
|
||
|
|
(reg & MQ200_GC1CRTC_GREEN_NOTLOADED)?"":"G",
|
||
|
|
(reg & MQ200_GC1CRTC_OUTPUT_LEVEL_MASK)>>MQ200_GC1CRTC_OUTPUT_LEVEL_SHIFT);
|
||
|
|
}
|
||
|
|
if (reg & MQ200_GC1CRTC_MONO)
|
||
|
|
printf("Mono_monitor ");
|
||
|
|
printf("\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC02R Horizontal Display Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHDCR(gc));
|
||
|
|
if (gc == 0) {
|
||
|
|
printf("GC02R=0x%08x: Horizontal display total=%03d end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GC1HDC_TOTAL_MASK)>>MQ200_GC1HDC_TOTAL_SHIFT,
|
||
|
|
(reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);
|
||
|
|
} else {
|
||
|
|
printf("GC02R=0x%08x: Horizontal display end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GCHDC_END_MASK)>>MQ200_GCHDC_END_SHIFT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC03R Vertical Display Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCVDCR(gc));
|
||
|
|
if (gc == 0) {
|
||
|
|
printf("GC03R=0x%08x: Vertical display total=%03d end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GC1VDC_TOTAL_MASK)>>MQ200_GC1VDC_TOTAL_SHIFT,
|
||
|
|
(reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);
|
||
|
|
} else {
|
||
|
|
printf("GC03R=0x%08x: Vertical display end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GCVDC_END_MASK)>>MQ200_GCVDC_END_SHIFT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC04R Horizontal Sync Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHSCR(gc));
|
||
|
|
printf("GC04R=0x%08x: Horizontal sync start=%03d end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GCHSC_START_MASK)>>MQ200_GCHSC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCHSC_END_MASK)>>MQ200_GCHSC_END_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC05R Vertical Sync Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCVSCR(gc));
|
||
|
|
printf("GC05R=0x%08x: Vertical sync start=%03d end=%03d\n", reg,
|
||
|
|
(reg&MQ200_GCVSC_START_MASK)>>MQ200_GCVSC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCVSC_END_MASK)>>MQ200_GCVSC_END_SHIFT);
|
||
|
|
|
||
|
|
if (gc == 0) {
|
||
|
|
/*
|
||
|
|
* GC07R Vertical Display Count
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GC1VDCNTR);
|
||
|
|
printf("GC07R=0x%08x: Vertical Display Count=%d\n", reg,
|
||
|
|
(reg&MQ200_GC1VDCNT_MASK));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC08R Window Horizontal Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCWHCR(gc));
|
||
|
|
printf("GC08R=0x%08x: Window Horizontal start=%03d width=%03d",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCWHC_START_MASK)>> MQ200_GCWHC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCWHC_WIDTH_MASK)>> MQ200_GCWHC_WIDTH_SHIFT);
|
||
|
|
if (gc == 0) {
|
||
|
|
printf(" add=%03x",
|
||
|
|
(reg&MQ200_GC1WHC_ALD_MASK)>> MQ200_GC1WHC_ALD_SHIFT);
|
||
|
|
}
|
||
|
|
printf("\n");
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC09R Window Vertical Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCWVCR(gc));
|
||
|
|
printf("GC09R=0x%08x: Window Vertical start=%03d hight=%03d\n",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCWVC_START_MASK)>> MQ200_GCWVC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCWVC_HEIGHT_MASK)>> MQ200_GCWVC_HEIGHT_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC0AR Alternate Window Horizontal Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCAWHCR(gc));
|
||
|
|
printf("GC0AR=0x%08x: Altwin Horizontal start=%03d width=%03d",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCAWHC_START_MASK)>> MQ200_GCAWHC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCAWHC_WIDTH_MASK)>> MQ200_GCAWHC_WIDTH_SHIFT);
|
||
|
|
if (gc == 0) {
|
||
|
|
printf(" add=%03d",
|
||
|
|
(reg&MQ200_GC1AWHC_ALD_MASK)>> MQ200_GC1AWHC_ALD_SHIFT);
|
||
|
|
}
|
||
|
|
printf("\n");
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC0BR Alternate Window Vertical Control
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCAWVCR(gc));
|
||
|
|
printf("GC0BR=0x%08x: Altwin Vertical start=%03d hight=%03d\n",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCAWVC_START_MASK)>> MQ200_GCAWVC_START_SHIFT,
|
||
|
|
(reg&MQ200_GCAWVC_HEIGHT_MASK)>> MQ200_GCAWVC_HEIGHT_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC0CR Window Start Address
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCWSAR(gc));
|
||
|
|
printf("GC0CR=0x%08x: Window start address=0x%08x\n",
|
||
|
|
reg, (reg&MQ200_GCWSA_MASK));
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC0DR Alternate Window Start Address
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCAWSAR(gc));
|
||
|
|
printf("GC0DR=0x%08x: Altwin start address=0x%08x palette_index=%02d\n",
|
||
|
|
reg, (reg&MQ200_GCAWSA_MASK),
|
||
|
|
(reg&MQ200_GCAWPI_MASK)>>MQ200_GCAWPI_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC0ER Windows Stride
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCWSTR(gc));
|
||
|
|
printf("GC0ER=0x%08x: Stride window=%04d altwin=%04d\n",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCWST_MASK)>>MQ200_GCWST_SHIFT,
|
||
|
|
(reg&MQ200_GCAWST_MASK)>>MQ200_GCAWST_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC10R Hardware Cursor Position
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHCPR(gc));
|
||
|
|
printf("GC10R=0x%08x: Hardware Cursor Position %d,%d\n",
|
||
|
|
reg,
|
||
|
|
(reg&MQ200_GCHCP_HSTART_MASK)>>MQ200_GCHCP_HSTART_SHIFT,
|
||
|
|
(reg&MQ200_GCHCP_VSTART_MASK)>>MQ200_GCHCP_VSTART_SHIFT);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC11R Hardware Cursor Start Address and Offset
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHCAOR(gc));
|
||
|
|
printf("GC11R=0x%08x: Hardware Cursor Start Address and Offset\n",
|
||
|
|
reg);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC12R Hardware Cursor Foreground Color
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHCFCR(gc));
|
||
|
|
printf("GC12R=0x%08x: Hardware Cursor Foreground Color\n", reg);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* GC13R Hardware Cursor Background Color
|
||
|
|
*/
|
||
|
|
reg = mq200_read(sc, MQ200_GCHCBCR(gc));
|
||
|
|
printf("GC13R=0x%08x: Hardware Cursor Background Color\n", reg);
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
mq200_dump_fp(struct mq200_softc *sc)
|
||
|
|
{
|
||
|
|
u_int32_t reg;
|
||
|
|
#define I(type) ((type)>>MQ200_FPC_TYPE_SHIFT)
|
||
|
|
static char *panel_type_names[64] = {
|
||
|
|
[I(MQ200_FPC_TFT4MONO)] = "TFT 4bit mono",
|
||
|
|
[I(MQ200_FPC_TFT12)] = "TFT 12bit color",
|
||
|
|
[I(MQ200_FPC_SSTN4)] = "S-STN 4bit color",
|
||
|
|
[I(MQ200_FPC_DSTN8)] = "D-STN 8bit color",
|
||
|
|
[I(MQ200_FPC_TFT6MONO)] = "TFT 6bit mono",
|
||
|
|
[I(MQ200_FPC_TFT18)] = "TFT 18bit color",
|
||
|
|
[I(MQ200_FPC_SSTN8)] = "S-STN 8bit color",
|
||
|
|
[I(MQ200_FPC_DSTN16)] = "D-STN 16bit color",
|
||
|
|
[I(MQ200_FPC_TFT8MONO)] = "TFT 8bit mono",
|
||
|
|
[I(MQ200_FPC_TFT24)] = "TFT 24bit color",
|
||
|
|
[I(MQ200_FPC_SSTN12)] = "S-STN 12bit color",
|
||
|
|
[I(MQ200_FPC_DSTN24)] = "D-STN 24bit color",
|
||
|
|
[I(MQ200_FPC_SSTN16)] = "S-STN 16bit color",
|
||
|
|
[I(MQ200_FPC_SSTN24)] = "S-STN 24bit color",
|
||
|
|
};
|
||
|
|
|
||
|
|
reg = mq200_read(sc, MQ200_FPCR);
|
||
|
|
printf("FP00R=0x%08x: Flat Panel Control\n", reg);
|
||
|
|
printf(" %s, driven by %s, %s\n",
|
||
|
|
ENABLE(reg & MQ200_FPC_ENABLE),
|
||
|
|
(reg & MQ200_FPC_GC2) ? "GC2" : "GC1",
|
||
|
|
panel_type_names[(reg & MQ200_FPC_TYPE_MASK) >> MQ200_FPC_TYPE_SHIFT]);
|
||
|
|
reg = mq200_read(sc, MQ200_FPPCR);
|
||
|
|
printf("FP01R=0x%08x: Flat Panel Output Pin Control\n", reg);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
mq200_dump_dc(struct mq200_softc *sc)
|
||
|
|
{
|
||
|
|
u_int32_t reg;
|
||
|
|
|
||
|
|
reg = 0;
|
||
|
|
}
|
||
|
|
#endif /* 0 */
|
||
|
|
|
||
|
|
#endif /* MQ200_DEBUG */
|