1997-10-09 11:57:17 +04:00
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/* $NetBSD: gusreg.h,v 1.6 1997/10/09 07:57:22 jtc Exp $ */
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1996-02-05 03:10:32 +03:00
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1995-07-19 23:58:09 +04:00
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/*-
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1996-02-05 03:10:32 +03:00
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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1995-07-19 23:58:09 +04:00
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* All rights reserved.
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*
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1996-02-05 03:10:32 +03:00
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ken Hornstein and John Kohl.
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1995-07-19 23:58:09 +04:00
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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1996-02-05 03:10:32 +03:00
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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1995-07-19 23:58:09 +04:00
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*
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1996-02-05 05:18:48 +03:00
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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1997-10-09 11:57:17 +04:00
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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1996-02-05 05:18:48 +03:00
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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1995-07-19 23:58:09 +04:00
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*/
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/*
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* Register definitions of Gravis UltraSound card
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*/
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/*
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* MIDI control registers. Essentially a MC6850 UART. Note the MC6850's
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* "feature" of having read-only and write-only registers combined on one
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* address.
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*/
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1997-09-06 18:23:13 +04:00
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#define GUS_IOH4_OFFSET 0x100
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#define GUS_NPORT4 2
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#define GUS_MIDI_CONTROL (0x100-GUS_IOH4_OFFSET)
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#define GUS_MIDI_STATUS (0x100-GUS_IOH4_OFFSET)
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#define GUS_MIDI_READ (0x101-GUS_IOH4_OFFSET)
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#define GUS_MIDI_WRITE (0x101-GUS_IOH4_OFFSET)
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1995-07-19 23:58:09 +04:00
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/*
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* Joystick interface - note this is an absolute address, NOT an offset from
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* the GUS base address.
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*/
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#define GUS_JOYSTICK 0x201
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/*
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* GUS control registers
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*/
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#define GUS_MIX_CONTROL 0x000
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#define GUS_IRQ_STATUS 0x006
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#define GUS_TIMER_CONTROL 0x008
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#define GUS_TIMER_DATA 0x009
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#define GUS_REG_CONTROL 0x00f /* rev 3.4 or later only: select reg
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at 2XB */
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#define GUS_REG_NORMAL 0x00 /* IRQ/DMA as usual */
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#define GUS_REG_IRQCTL 0x05 /* IRQ ctl: write 0 to clear IRQ state */
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#define GUS_REG_JUMPER 0x06 /* jumper control: */
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#define GUS_JUMPER_MIDIEN 0x02 /* bit: enable MIDI ports */
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#define GUS_JUMPER_JOYEN 0x04 /* bit: enable joystick ports */
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#define GUS_IRQ_CONTROL 0x00b
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#define GUS_DMA_CONTROL 0x00b
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#define GUS_IRQCTL_CONTROL 0x00b
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#define GUS_JUMPER_CONTROL 0x00b
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1997-09-06 18:23:13 +04:00
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#define GUS_NPORT1 16
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#define GUS_IOH2_OFFSET 0x102
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#define GUS_VOICE_SELECT (0x102-GUS_IOH2_OFFSET)
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#define GUS_REG_SELECT (0x103-GUS_IOH2_OFFSET)
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#define GUS_DATA_LOW (0x104-GUS_IOH2_OFFSET)
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#define GUS_DATA_HIGH (0x105-GUS_IOH2_OFFSET)
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/* GUS_MIXER_SELECT 106 */
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#define GUS_DRAM_DATA (0x107-GUS_IOH2_OFFSET)
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#define GUS_NPORT2 6
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1995-07-19 23:58:09 +04:00
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/*
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* GUS on-board global registers
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*/
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#define GUSREG_DMA_CONTROL 0x41
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#define GUSREG_DMA_START 0x42
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#define GUSREG_DRAM_ADDR_LOW 0x43
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#define GUSREG_DRAM_ADDR_HIGH 0x44
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#define GUSREG_TIMER_CONTROL 0x45
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#define GUSREG_TIMER1_COUNT 0x46 /* count-up, then interrupt, 80usec */
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#define GUSREG_TIMER2_COUNT 0x47 /* count-up, then interrupt, 320usec */
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#define GUSREG_SAMPLE_FREQ 0x48 /* 9878400/(16*(rate+2)) */
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#define GUSREG_SAMPLE_CONTROL 0x49
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#define GUSREG_JOYSTICK_TRIM 0x4b
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#define GUSREG_RESET 0x4c
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/*
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* GUS voice specific registers (some of which aren't!). Add 0x80 to these
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* registers for reads
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*/
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#define GUSREG_READ 0x80
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#define GUSREG_VOICE_CNTL 0x00
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#define GUSREG_FREQ_CONTROL 0x01
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#define GUSREG_START_ADDR_HIGH 0x02
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#define GUSREG_START_ADDR_LOW 0x03
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#define GUSREG_END_ADDR_HIGH 0x04
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#define GUSREG_END_ADDR_LOW 0x05
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#define GUSREG_VOLUME_RATE 0x06
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#define GUSREG_START_VOLUME 0x07
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#define GUSREG_END_VOLUME 0x08
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#define GUSREG_CUR_VOLUME 0x09
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#define GUSREG_CUR_ADDR_HIGH 0x0a
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#define GUSREG_CUR_ADDR_LOW 0x0b
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#define GUSREG_PAN_POS 0x0c
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#define GUSREG_VOLUME_CONTROL 0x0d
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#define GUSREG_ACTIVE_VOICES 0x0e /* voice-independent:set voice count */
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#define GUSREG_IRQ_STATUS 0x8f /* voice-independent */
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#define GUS_PAN_FULL_LEFT 0x0
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#define GUS_PAN_FULL_RIGHT 0xf
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/*
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* GUS Bitmasks for reset register
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*/
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#define GUSMASK_MASTER_RESET 0x01
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#define GUSMASK_DAC_ENABLE 0x02
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#define GUSMASK_IRQ_ENABLE 0x04
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/*
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* Bitmasks for IRQ status port
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*/
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#define GUSMASK_IRQ_MIDIXMIT 0x01 /* MIDI transmit IRQ */
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#define GUSMASK_IRQ_MIDIRCVR 0x02 /* MIDI received IRQ */
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#define GUSMASK_IRQ_TIMER1 0x04 /* timer 1 IRQ */
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#define GUSMASK_IRQ_TIMER2 0x08 /* timer 2 IRQ */
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#define GUSMASK_IRQ_RESERVED 0x10 /* Reserved (set to 0) */
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#define GUSMASK_IRQ_VOICE 0x20 /* Wavetable IRQ (any voice) */
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#define GUSMASK_IRQ_VOLUME 0x40 /* Volume ramp IRQ (any voc) */
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#define GUSMASK_IRQ_DMATC 0x80 /* DMA transfer complete */
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/*
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* Bitmasks for sampling control register
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*/
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#define GUSMASK_SAMPLE_START 0x01 /* start sampling */
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#define GUSMASK_SAMPLE_STEREO 0x02 /* mono or stereo */
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#define GUSMASK_SAMPLE_DATA16 0x04 /* 16-bit DMA channel */
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#define GUSMASK_SAMPLE_IRQ 0x20 /* enable IRQ */
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#define GUSMASK_SAMPLE_DMATC 0x40 /* DMA transfer complete */
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#define GUSMASK_SAMPLE_INVBIT 0x80 /* invert MSbit */
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/*
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* Bitmasks for IRQ status register (different than IRQ status _port_ - the
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* register is internal to the GUS)
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*/
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#define GUSMASK_WIRQ_VOLUME 0x40 /* Flag for volume interrupt */
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#define GUSMASK_WIRQ_VOICE 0x80 /* Flag for voice interrupt */
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#define GUSMASK_WIRQ_VOICEMASK 0x1f /* Bits holding voice # */
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/*
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* GUS bitmasks for built-in mixer control (separate from the ICS or CS chips)
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*/
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#define GUSMASK_LINE_IN 0x01 /* 0=enable */
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#define GUSMASK_LINE_OUT 0x02 /* 0=enable */
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#define GUSMASK_MIC_IN 0x04 /* 1=enable */
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#define GUSMASK_LATCHES 0x08 /* enable IRQ latches */
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#define GUSMASK_COMBINE 0x10 /* combine Ch 1 IRQ & Ch 2 (MIDI) */
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#define GUSMASK_MIDI_LOOPBACK 0x20 /* MIDI loopback */
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#define GUSMASK_CONTROL_SEL 0x40 /* Select control register */
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#define GUSMASK_BOTH_RQ 0x40 /* Combine both RQ lines */
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/*
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* GUS bitmaks for DMA control
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*/
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#define GUSMASK_DMA_ENABLE 0x01 /* Enable DMA transfer */
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#define GUSMASK_DMA_READ 0x02 /* 1=read, 0=write */
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#define GUSMASK_DMA_WRITE 0x00 /* for consistancy */
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#define GUSMASK_DMA_WIDTH 0x04 /* Data transfer width */
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#define GUSMASK_DMA_R0 0x00 /* Various DMA speeds */
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#define GUSMASK_DMA_R1 0x08
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#define GUSMASK_DMA_R2 0x10
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#define GUSMASK_DMA_R3 0x18
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#define GUSMASK_DMA_IRQ 0x20 /* Enable DMA to IRQ */
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#define GUSMASK_DMA_IRQPEND 0x40 /* DMA IRQ pending */
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#define GUSMASK_DMA_DATA_SIZE 0x40 /* 0=8 bit, 1=16 bit */
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#define GUSMASK_DMA_INVBIT 0x80 /* invert high bit */
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/*
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* GUS bitmasks for voice control
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*/
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#define GUSMASK_VOICE_STOPPED 0x01 /* The voice is stopped */
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#define GUSMASK_STOP_VOICE 0x02 /* Force voice to stop */
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#define GUSMASK_DATA_SIZE16 0x04 /* 1=16 bit, 0=8 bit data */
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#define GUSMASK_LOOP_ENABLE 0x08 /* Loop voice at end */
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#define GUSMASK_VOICE_BIDIR 0x10 /* Bi-directional looping */
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#define GUSMASK_VOICE_IRQ 0x20 /* Enable the voice IRQ */
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#define GUSMASK_INCR_DIR 0x40 /* Direction of address incr */
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#define GUSMASK_VOICE_IRQPEND 0x80 /* Pending IRQ for voice */
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/*
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* Bitmasks for volume control
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*/
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#define GUSMASK_VOLUME_STOPPED 0x01 /* Volume ramping stopped */
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#define GUSMASK_STOP_VOLUME 0x02 /* Manually stop volume */
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#define GUSMASK_VOICE_ROLL 0x04 /* Roll over/low water condition */
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#define GUSMASK_VOLUME_LOOP 0x08 /* Volume ramp looping */
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#define GUSMASK_VOLUME_BIDIR 0x10 /* Bi-dir volume looping */
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#define GUSMASK_VOLUME_IRQ 0x20 /* IRQ on end of volume ramp */
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#define GUSMASK_VOLUME_DIR 0x40 /* Direction of volume ramp */
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#define GUSMASK_VOLUME_IRQPEND 0x80 /* Pending volume IRQ */
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#define MIDI_RESET 0x03
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/*
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* ICS Mixer registers
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*/
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1997-09-06 18:23:13 +04:00
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#define GUS_IOH3_OFFSET 0x506
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#define GUS_NPORT3 1
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#define GUS_MIXER_SELECT (0x506-GUS_IOH3_OFFSET) /* read=board rev, wr=mixer */
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#define GUS_BOARD_REV (0x506-GUS_IOH3_OFFSET)
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#define GUS_MIXER_DATA (0x106-GUS_IOH2_OFFSET) /* data for mixer control */
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1995-07-19 23:58:09 +04:00
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#define GUSMIX_CHAN_MIC ICSMIX_CHAN_0
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#define GUSMIX_CHAN_LINE ICSMIX_CHAN_1
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#define GUSMIX_CHAN_CD ICSMIX_CHAN_2
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#define GUSMIX_CHAN_DAC ICSMIX_CHAN_3
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#define GUSMIX_CHAN_MASTER ICSMIX_CHAN_5
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/*
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* Codec/Mixer registers
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*/
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1997-03-19 09:45:21 +03:00
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#define GUS_MAX_CODEC_BASE 0x10C
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#define GUS_DAUGHTER_CODEC_BASE 0x530
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#define GUS_DAUGHTER_CODEC_BASE2 0x604
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#define GUS_DAUGHTER_CODEC_BASE3 0xE80
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#define GUS_DAUGHTER_CODEC_BASE4 0xF40
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#define GUS_CODEC_SELECT 0
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#define GUS_CODEC_DATA 1
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#define GUS_CODEC_STATUS 2
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#define GUS_CODEC_PIO 3
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1995-07-19 23:58:09 +04:00
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#define GUS_MAX_CTRL 0x106
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#define GUS_MAX_BASEBITS 0xf /* sets middle nibble of 3X6 */
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#define GUS_MAX_RECCHAN16 0x10 /* 0=8bit DMA read, 1=16bit DMA read */
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#define GUS_MAX_PLAYCHAN16 0x20 /* 0=8bit, 1=16bit */
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#define GUS_MAX_CODEC_ENABLE 0x40 /* 0=disable, 1=enable */
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