377 lines
12 KiB
C
377 lines
12 KiB
C
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#include "ite.h"
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#if NITE > 0
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#include "param.h"
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#include "conf.h"
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#include "proc.h"
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#include "ioctl.h"
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#include "tty.h"
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#include "systm.h"
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#include "itevar.h"
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#include "machine/cpu.h"
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/* XXX */
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#include "grfioctl.h"
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#include "grfvar.h"
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#include "grf_rtreg.h"
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void retina_init(struct ite_softc *ip)
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{
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struct MonDef *md;
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if (ip->grf == 0)
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ip->grf = &grf_softc[ip - ite_softc];
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ip->priv = ip->grf->g_display.gd_regaddr;
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md = (struct MonDef *) ip->priv;
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ip->cols = md->TX;
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ip->rows = md->TY;
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}
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void retina_cursor(struct ite_softc *ip, int flag)
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{
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volatile u_char *ba = ip->grf->g_regkva;
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if (flag == ERASE_CURSOR)
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{
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/* disable cursor */
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WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) | 0x20);
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}
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else
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{
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int pos = ip->curx + ip->cury * ip->cols;
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/* make sure to enable cursor */
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WCrt (ba, CRT_ID_CURSOR_START, RCrt (ba, CRT_ID_CURSOR_START) & ~0x20);
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/* and position it */
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WCrt (ba, CRT_ID_CURSOR_LOC_HIGH, (u_char) (pos >> 8));
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WCrt (ba, CRT_ID_CURSOR_LOC_LOW, (u_char) pos);
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ip->cursorx = ip->curx;
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ip->cursory = ip->cury;
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}
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}
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static void screen_up (struct ite_softc *ip, int top, int bottom, int lines)
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{
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volatile u_char * ba = ip->grf->g_regkva;
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volatile u_char * fb = ip->grf->g_fbkva;
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const struct MonDef * md = (struct MonDef *) ip->priv;
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/* do some bounds-checking here.. */
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if (top >= bottom)
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return;
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if (top + lines >= bottom)
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{
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retina_clear (ip, top, 0, bottom - top, ip->cols);
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return;
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}
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/* the trick here is to use a feature of the NCR chip. It can
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optimize data access in various read/write modes. One of
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the modes is able to read/write from/to different zones.
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Thus, by setting the read-offset to lineN, and the write-offset
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to line0, we just cause read/write cycles for all characters
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up to the last line, and have the chip transfer the data. The
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`addqb' are the cheapest way to cause read/write cycles (DONT
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use `tas' on the Amiga!), their results are completely ignored
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by the NCR chip, it just replicates what it just read. */
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/* write to primary, read from secondary */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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/* write to line TOP */
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long toploc = top * (md->TX / 16);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toploc));
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toploc >> 8)));
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}
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{
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/* read from line TOP + LINES */
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long fromloc = (top+lines) * (md->TX / 16);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc)) ;
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
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}
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{
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unsigned char * p = (unsigned char *) fb;
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/* transfer all characters but LINES lines, unroll by 16 */
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short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
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do {
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@+" : "=a" (p) : "0" (p));
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} while (x--);
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}
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/* reset to default values */
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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/* read/write to primary on A0, secondary on B0 */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 );
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/* fill the free lines with spaces */
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{ /* feed latches with value */
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unsigned short * f = (unsigned short *) fb;
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f += (1 + bottom - lines) * md->TX * 2;
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*f = 0x2010;
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{
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volatile unsigned short dummy = *((volatile unsigned short *)f);
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}
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}
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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unsigned long * p = (unsigned long *) fb;
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short x = (lines * (md->TX/16)) - 1;
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const unsigned long dummyval = 0;
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p += (1 + bottom - lines) * (md->TX/4);
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do {
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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} while (x--);
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}
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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};
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static void screen_down (struct ite_softc *ip, int top, int bottom, int lines)
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{
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volatile u_char * ba = ip->grf->g_regkva;
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volatile u_char * fb = ip->grf->g_fbkva;
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const struct MonDef * md = (struct MonDef *) ip->priv;
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/* do some bounds-checking here.. */
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if (top >= bottom)
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return;
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if (top + lines >= bottom)
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{
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retina_clear (ip, top, 0, bottom - top, ip->cols);
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return;
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}
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/* see screen_up() for explanation of chip-tricks */
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/* write to primary, read from secondary */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0 );
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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/* write to line TOP + LINES */
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long toloc = (top + lines) * (md->TX / 16);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, ((unsigned char)toloc));
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, ((unsigned char)(toloc >> 8)));
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}
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{
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/* read from line TOP */
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long fromloc = top * (md->TX / 16);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, ((unsigned char)fromloc));
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, ((unsigned char)(fromloc >> 8))) ;
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}
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{
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unsigned char * p = (unsigned char *) fb;
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short x = (1 + bottom - (top + lines)) * (md->TX / 16) - 1;
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p += (1 + bottom - (top + lines)) * md->TX;
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do {
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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asm volatile("addqb #1,%0@-" : "=a" (p) : "0" (p));
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} while (x--);
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}
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_PRIM_HOST_OFF_LO, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_HI, 0);
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WSeq (ba, SEQ_ID_SEC_HOST_OFF_LO, 0);
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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/* read/write to primary on A0, secondary on B0 */
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WSeq (ba, SEQ_ID_EXTENDED_MEM_ENA, (RSeq(ba, SEQ_ID_EXTENDED_MEM_ENA) & 0x1f) | 0x40 );
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/* fill the free lines with spaces */
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{ /* feed latches with value */
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unsigned short * f = (unsigned short *) fb;
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f += top * md->TX * 2;
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*f = 0x2010;
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{
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volatile unsigned short dummy = *((volatile unsigned short *)f);
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}
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}
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/* clear extended chain4 mode */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR, RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) & ~0x02);
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/* set write mode 1, "[...] data in the read latches is written
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to memory during CPU memory write cycles. [...]" */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 1);
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{
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unsigned long * p = (unsigned long *) fb;
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short x = (lines * (md->TX/16)) - 1;
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const unsigned long dummyval = 0;
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p += top * (md->TX/4);
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do {
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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*p++ = dummyval;
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} while (x--);
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}
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/* write mode 0 */
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WGfx (ba, GCT_ID_GRAPHICS_MODE, (RGfx(ba, GCT_ID_GRAPHICS_MODE) & 0xfc) | 0);
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/* extended chain4 enable */
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WSeq (ba, SEQ_ID_EXT_VIDEO_ADDR , RSeq(ba, SEQ_ID_EXT_VIDEO_ADDR) | 0x02);
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};
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void retina_deinit(struct ite_softc *ip)
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{
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ip->flags &= ~ITE_INITED;
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}
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void retina_putc(struct ite_softc *ip, int c, int dy, int dx, int mode)
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{
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volatile u_char * ba = ip->grf->g_regkva;
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volatile u_char * fb = ip->grf->g_fbkva;
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register u_char attr;
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attr = (mode & ATTR_INV) ? 0x21 : 0x10;
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if (mode & ATTR_UL) attr = 0x01; /* ???????? */
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if (mode & ATTR_BOLD) attr |= 0x08;
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|
if (mode & ATTR_BLINK) attr |= 0x80;
|
||
|
|
|
||
|
|
fb += 4 * (dy * ip->cols + dx);
|
||
|
|
*fb++ = c; *fb = attr;
|
||
|
|
}
|
||
|
|
|
||
|
|
void retina_clear(struct ite_softc *ip, int sy, int sx, int h, int w)
|
||
|
|
{
|
||
|
|
volatile u_char * ba = ip->grf->g_regkva;
|
||
|
|
u_short * fb = (u_short *) ip->grf->g_fbkva;
|
||
|
|
short x;
|
||
|
|
const u_short fillval = 0x2010;
|
||
|
|
/* could probably be optimized just like the scrolling functions !! */
|
||
|
|
fb += 2 * (sy * ip->cols + sx);
|
||
|
|
while (h--)
|
||
|
|
{
|
||
|
|
for (x = 2 * (w - 1); x >= 0; x -= 2)
|
||
|
|
fb[x] = fillval;
|
||
|
|
fb += 2 * ip->cols;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void retina_scroll(struct ite_softc *ip, int sy, int sx, int count, int dir)
|
||
|
|
{
|
||
|
|
volatile u_char * ba = ip->grf->g_regkva;
|
||
|
|
u_long * fb = (u_short *) ip->grf->g_fbkva;
|
||
|
|
register int height, dy, i;
|
||
|
|
|
||
|
|
retina_cursor(ip, ERASE_CURSOR);
|
||
|
|
|
||
|
|
if (dir == SCROLL_UP)
|
||
|
|
{
|
||
|
|
screen_up (ip, sy - count, ip->bottom_margin, count);
|
||
|
|
/* bcopy (fb + sy * ip->cols, fb + (sy - count) * ip->cols, 4 * (ip->bottom_margin - sy + 1) * ip->cols); */
|
||
|
|
/* retina_clear (ip, ip->bottom_margin + 1 - count, 0, count, ip->cols); */
|
||
|
|
}
|
||
|
|
else if (dir == SCROLL_DOWN)
|
||
|
|
{
|
||
|
|
screen_down (ip, sy, ip->bottom_margin, count);
|
||
|
|
/* bcopy (fb + sy * ip->cols, fb + (sy + count) * ip->cols, 4 * (ip->bottom_margin - sy - count + 1) * ip->cols); */
|
||
|
|
/* retina_clear (ip, sy, 0, count, ip->cols); */
|
||
|
|
}
|
||
|
|
else if (dir == SCROLL_RIGHT)
|
||
|
|
{
|
||
|
|
bcopy (fb + sx + sy * ip->cols, fb + sx + sy * ip->cols + count, 4 * (ip->cols - (sx + count)));
|
||
|
|
retina_clear (ip, sy, sx, 1, count);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
bcopy (fb + sx + sy * ip->cols, fb + sx - count + sy * ip->cols, 4 * (ip->cols - sx));
|
||
|
|
retina_clear (ip, sy, ip->cols - count, 1, count);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
|