81 lines
3.4 KiB
C
81 lines
3.4 KiB
C
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/* SWI veneers:
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* Written by Edward Nevill and Jonathan Roach in an idle moment between projects.
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* Hacked by BDB to add flag returning
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*/
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/* Anonymous Error type */
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struct Error { int num; char msg[4]; };
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typedef struct Error Error;
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/* Generic SWI interface
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* swi(swino,mask,regs...)
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* swino = SWI number to call as defined in h.swis, X bit set if you wish the
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* X form of the SWI to be called, clear if you want the non X form.
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* reg_mask = mask of in / out registers
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* bits 0-9: Bit N set => Register N specified on input
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* Bit N clear => Register N unspecified on input
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* bits 22-31: Bit N set => Register N-22 on output stored
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* in address specified in varargs list.
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* ... In order, input registers followed by output registers,
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* starting at r0 and going up.
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* returns 0 or errorblock pointer if X-bit set
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* returns r0 if X-bit clear
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* swix(swino,mask,regs...)
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* This behaves identically to 'swi' except that it always calls the X form.
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*
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* Eg:
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* swi(OS_SWINumberToString, IN(R0|R1|R2), n, buf, 255);
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* e = swi(XOS_SWINumberFromString, IN(R1)|OUT(R0), str, &n);
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* - Error block pointer (or 0) is returned so must get returned R0
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* - via argument list.
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* e = swix(OS_SWINumberFromString, IN(R1)|OUT(R0), str, &n);
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* - As above but uses the swix function rather that setting the X bit
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* explicitly (saves one instruction on SWI call).
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* e = swi(OS_File, IN(R0|R1|R2|R3)|OUT(R4), 255, name, buff, 0, &len);
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* - We don't care about the load, exec or attrs so don't specify
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* them in the output registers.
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*/
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extern Error *swix(int swino, int reg_mask, ...);
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extern int swi(int swino, int reg_mask, ...);
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/* Register mask macros
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* The bits in the register mask are arranged as follows:
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* 31 30 29 ... 22 ... 8 ... 2 1 0
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* O0 O1 O2 ... O9 I9 ... I2 I1 I0 I(N) = bit set if R(N) used on entry
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* O(N) = bit set if R(N) written on exit
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* The bits are arranged like this to optimise the case where a SWI is being
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* called with a small number of input and output registers. For example, a SWI
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* call which uses R0-R5 on entry and R0-R1 on exit will have a register mask
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* of 0xC000003f which can be loaded into an ARM register in one instruction
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* (the compiler performs this optimisation, even when the constant wraps
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* around between bits 0 and 31). Using the more obvious coding of I0-I9 in bits
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* 0 - 9 and O0-O9 in bits 16-23 leads to a constant of 0x0003003f which require
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* two instructions.
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*/
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#define IN(m) (m)
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/* old, incorrect version
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#define OUT(m) ((unsigned)(m&1)<<31|(m&2)<<29|(m&4)<<27|(m&8)<<25|(m&16)<<23|\
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(m&32)<<21|(m&64)<<19|(m&128)<<17|(m&256)<<15|(m&512)<<13)
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*/
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#define OUT(m) ((unsigned)((m)&1)<<31|((m)&2)<<29|((m)&4)<<27|\
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((m)&8)<<25|((m)&16)<<23|((m)&32)<<21|((m)&64)<<19|\
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((m)&128)<<17|((m)&256)<<15|((m)&512)<<13|((m)&1024)<<11)
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/* The register names
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* Change these to use different names if you use R0 - R9 elsewhere in your program
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*/
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#define PSW 0x400 /* Use only in OUT, orders BEFORE others */
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#define R0 0x001
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#define R1 0x002
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#define R2 0x004
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#define R3 0x008
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#define R4 0x010
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#define R5 0x020
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#define R6 0x040
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#define R7 0x080
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#define R8 0x100
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#define R9 0x200
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