137 lines
4.0 KiB
C
137 lines
4.0 KiB
C
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/* $NetBSD: becc_intr.h,v 1.1 2003/01/25 01:57:18 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BECC_INTR_H_
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#define _BECC_INTR_H_
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#include <arm/armreg.h>
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#include <arm/cpufunc.h>
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#include <arm/xscale/beccreg.h>
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#include <arm/xscale/becc_csrvar.h>
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static __inline void __attribute__((__unused__))
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becc_set_intrmask(void)
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{
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extern __volatile uint32_t intr_enabled;
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/*
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* The bits in the ICMR indicate which interrupts are masked
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* (disabled), so we must invert our intr_enabled mask.
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*/
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BECC_CSR_WRITE(BECC_ICMR, ~intr_enabled & ICU_VALID_MASK);
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(void) BECC_CSR_READ(BECC_ICMR);
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}
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static __inline int __attribute__((__unused__))
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becc_splraise(int ipl)
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{
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extern __volatile uint32_t current_spl_level;
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extern uint32_t becc_imask[];
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uint32_t old;
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old = current_spl_level;
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current_spl_level |= becc_imask[ipl];
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return (old);
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}
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static __inline void __attribute__((__unused__))
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becc_splx(int new)
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{
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extern __volatile uint32_t intr_enabled, becc_ipending;
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extern __volatile uint32_t current_spl_level;
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uint32_t oldirqstate, hwpend;
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current_spl_level = new;
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/*
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* If there are pending HW interrupts which are being
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* unmasked, then enable them in the ICMR register.
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* This will cause them to come flooding in. This
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* includes soft interrupts.
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*/
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hwpend = becc_ipending & ~new;
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if (hwpend != 0) {
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oldirqstate = disable_interrupts(I32_bit);
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intr_enabled |= hwpend;
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becc_set_intrmask();
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restore_interrupts(oldirqstate);
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}
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}
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static __inline int __attribute__((__unused__))
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becc_spllower(int ipl)
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{
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extern __volatile uint32_t current_spl_level;
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extern uint32_t becc_imask[];
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uint32_t old = current_spl_level;
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becc_splx(becc_imask[ipl]);
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return (old);
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}
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static __inline void __attribute__((__unused__))
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becc_setsoftintr(int si)
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{
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extern __volatile uint32_t becc_sipending;
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becc_sipending |= (1 << si);
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BECC_CSR_WRITE(BECC_ICSR, (1U << ICU_SOFT));
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}
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int becc_softint(void *arg);
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#if !defined(EVBARM_SPL_NOINLINE)
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#define _splraise(ipl) becc_splraise(ipl)
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#define splx(new) becc_splx(new)
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#define _spllower(ipl) becc_spllower(ipl)
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#define _setsoftintr(si) becc_setsoftintr(si)
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#else
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int _splraise(int);
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void splx(int);
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int _spllower(int);
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void _setsoftintr(int);
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#endif /* ! EVBARM_SPL_NOINLINE */
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#endif /* _BECC_INTR_H_ */
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