1999-06-28 05:20:43 +04:00
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/* $NetBSD: vreset.c,v 1.4 1999/06/28 01:20:45 sakamoto Exp $ */
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1998-01-16 07:17:36 +03:00
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/*
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* Copyright (C) 1995-1997 Gary Thomas (gdt@linuxppc.org)
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* All rights reserved.
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*
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* Initialize the VGA control registers to 80x25 text mode.
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*
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* Adapted from a program by:
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* Steve Sellgren
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* San Francisco Indigo Company
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* sfindigo!sellgren@uunet.uu.net
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* Adapted for Moto boxes by:
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* Pat Kane & Mark Scott, 1996
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* Fixed for IBM/PowerStack II Pat Kane 1997
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gary Thomas.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifdef CONS_VGA
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1999-06-28 05:20:43 +04:00
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#include <stand.h>
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#include <machine/bswap.h>
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#include "boot.h"
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#include "iso_font.h"
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#if 0
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1998-01-16 07:17:36 +03:00
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static char rcsid[] = "vreset.c 2.0 1997 kane PEK'97 Exp $";
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#endif
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/*
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* VGA Register
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*/
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struct VgaRegs
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{
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1999-06-28 05:20:43 +04:00
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u_short io_port;
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u_char io_index;
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u_char io_value;
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1998-01-16 07:17:36 +03:00
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};
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/*
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* Default console text mode registers used to reset
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* graphics adapter.
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*/
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#define NREGS 54
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#define ENDMK 0xFFFF /* End marker */
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#define S3Vendor 0x5333
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#define CirrusVendor 0x1013
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#define DiamondVendor 0x100E
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#define MatroxVendor 0x102B
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struct VgaRegs GenVgaTextRegs[NREGS+1] = {
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/* port index value */
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/* SR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3c4, 0x1, 0x0 },
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{ 0x3c4, 0x2, 0x3 },
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{ 0x3c4, 0x3, 0x0 },
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{ 0x3c4, 0x4, 0x2 },
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1998-01-16 07:17:36 +03:00
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/* CR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3d4, 0x0, 0x5f },
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{ 0x3d4, 0x1, 0x4f },
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{ 0x3d4, 0x2, 0x50 },
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{ 0x3d4, 0x3, 0x82 },
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{ 0x3d4, 0x4, 0x55 },
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{ 0x3d4, 0x5, 0x81 },
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{ 0x3d4, 0x6, 0xbf },
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{ 0x3d4, 0x7, 0x1f },
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{ 0x3d4, 0x8, 0x00 },
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{ 0x3d4, 0x9, 0x4f },
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{ 0x3d4, 0xa, 0x0d },
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{ 0x3d4, 0xb, 0x0e },
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{ 0x3d4, 0xc, 0x00 },
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{ 0x3d4, 0xd, 0x00 },
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{ 0x3d4, 0xe, 0x00 },
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{ 0x3d4, 0xf, 0x00 },
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{ 0x3d4, 0x10, 0x9c },
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{ 0x3d4, 0x11, 0x8e },
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{ 0x3d4, 0x12, 0x8f },
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{ 0x3d4, 0x13, 0x28 },
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{ 0x3d4, 0x14, 0x1f },
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{ 0x3d4, 0x15, 0x96 },
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{ 0x3d4, 0x16, 0xb9 },
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{ 0x3d4, 0x17, 0xa3 },
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1998-01-16 07:17:36 +03:00
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/* GR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3ce, 0x0, 0x0 },
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{ 0x3ce, 0x1, 0x0 },
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{ 0x3ce, 0x2, 0x0 },
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{ 0x3ce, 0x3, 0x0 },
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{ 0x3ce, 0x4, 0x0 },
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{ 0x3ce, 0x5, 0x10 },
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{ 0x3ce, 0x6, 0xe },
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{ 0x3ce, 0x7, 0x0 },
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{ 0x3ce, 0x8, 0xff },
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{ ENDMK },
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1998-01-16 07:17:36 +03:00
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};
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struct VgaRegs S3TextRegs[NREGS+1] = {
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/* port index value */
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/* SR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3c4, 0x1, 0x0 },
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{ 0x3c4, 0x2, 0x3 },
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{ 0x3c4, 0x3, 0x0 },
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{ 0x3c4, 0x4, 0x2 },
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1998-01-16 07:17:36 +03:00
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/* CR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3d4, 0x0, 0x5f },
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{ 0x3d4, 0x1, 0x4f },
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{ 0x3d4, 0x2, 0x50 },
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{ 0x3d4, 0x3, 0x82 },
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{ 0x3d4, 0x4, 0x55 },
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{ 0x3d4, 0x5, 0x81 },
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{ 0x3d4, 0x6, 0xbf },
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{ 0x3d4, 0x7, 0x1f },
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{ 0x3d4, 0x8, 0x00 },
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{ 0x3d4, 0x9, 0x4f },
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{ 0x3d4, 0xa, 0x0d },
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{ 0x3d4, 0xb, 0x0e },
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{ 0x3d4, 0xc, 0x00 },
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{ 0x3d4, 0xd, 0x00 },
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{ 0x3d4, 0xe, 0x00 },
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{ 0x3d4, 0xf, 0x00 },
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{ 0x3d4, 0x10, 0x9c },
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{ 0x3d4, 0x11, 0x8e },
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{ 0x3d4, 0x12, 0x8f },
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{ 0x3d4, 0x13, 0x28 },
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{ 0x3d4, 0x14, 0x1f },
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{ 0x3d4, 0x15, 0x96 },
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{ 0x3d4, 0x16, 0xb9 },
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{ 0x3d4, 0x17, 0xa3 },
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1998-01-16 07:17:36 +03:00
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/* GR Regs */
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1999-06-28 05:20:43 +04:00
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{ 0x3ce, 0x0, 0x0 },
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{ 0x3ce, 0x1, 0x0 },
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{ 0x3ce, 0x2, 0x0 },
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{ 0x3ce, 0x3, 0x0 },
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{ 0x3ce, 0x4, 0x0 },
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{ 0x3ce, 0x5, 0x10 },
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{ 0x3ce, 0x6, 0xe },
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{ 0x3ce, 0x7, 0x0 },
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{ 0x3ce, 0x8, 0xff },
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{ ENDMK }
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1998-01-16 07:17:36 +03:00
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};
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struct RGBColors
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{
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1999-06-28 05:20:43 +04:00
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u_char r, g, b;
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1998-01-16 07:17:36 +03:00
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};
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/*
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* Default console text mode color table.
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* These values were obtained by booting Linux with
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* text mode firmware & then dumping the registers.
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*/
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struct RGBColors TextCLUT[256] =
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{
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/* red green blue */
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1999-06-28 05:20:43 +04:00
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{ 0x0, 0x0, 0x0 },
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{ 0x0, 0x0, 0x2a },
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{ 0x0, 0x2a, 0x0 },
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{ 0x0, 0x2a, 0x2a },
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{ 0x2a, 0x0, 0x0 },
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{ 0x2a, 0x0, 0x2a },
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{ 0x2a, 0x2a, 0x0 },
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{ 0x2a, 0x2a, 0x2a },
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{ 0x0, 0x0, 0x15 },
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{ 0x0, 0x0, 0x3f },
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{ 0x0, 0x2a, 0x15 },
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{ 0x0, 0x2a, 0x3f },
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{ 0x2a, 0x0, 0x15 },
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{ 0x2a, 0x0, 0x3f },
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{ 0x2a, 0x2a, 0x15 },
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{ 0x2a, 0x2a, 0x3f },
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{ 0x0, 0x15, 0x0 },
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{ 0x0, 0x15, 0x2a },
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{ 0x0, 0x3f, 0x0 },
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{ 0x0, 0x3f, 0x2a },
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{ 0x2a, 0x15, 0x0 },
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{ 0x2a, 0x15, 0x2a },
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{ 0x2a, 0x3f, 0x0 },
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{ 0x2a, 0x3f, 0x2a },
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{ 0x0, 0x15, 0x15 },
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{ 0x0, 0x15, 0x3f },
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{ 0x0, 0x3f, 0x15 },
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{ 0x0, 0x3f, 0x3f },
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{ 0x2a, 0x15, 0x15 },
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{ 0x2a, 0x15, 0x3f },
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{ 0x2a, 0x3f, 0x15 },
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{ 0x2a, 0x3f, 0x3f },
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{ 0x15, 0x0, 0x0 },
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{ 0x15, 0x0, 0x2a },
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{ 0x15, 0x2a, 0x0 },
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{ 0x15, 0x2a, 0x2a },
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{ 0x3f, 0x0, 0x0 },
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{ 0x3f, 0x0, 0x2a },
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{ 0x3f, 0x2a, 0x0 },
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{ 0x3f, 0x2a, 0x2a },
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{ 0x15, 0x0, 0x15 },
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{ 0x15, 0x0, 0x3f },
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{ 0x15, 0x2a, 0x15 },
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{ 0x15, 0x2a, 0x3f },
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{ 0x3f, 0x0, 0x15 },
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{ 0x3f, 0x0, 0x3f },
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{ 0x3f, 0x2a, 0x15 },
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{ 0x3f, 0x2a, 0x3f },
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{ 0x15, 0x15, 0x0 },
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{ 0x15, 0x15, 0x2a },
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{ 0x15, 0x3f, 0x0 },
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{ 0x15, 0x3f, 0x2a },
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{ 0x3f, 0x15, 0x0 },
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{ 0x3f, 0x15, 0x2a },
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{ 0x3f, 0x3f, 0x0 },
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{ 0x3f, 0x3f, 0x2a },
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{ 0x15, 0x15, 0x15 },
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{ 0x15, 0x15, 0x3f },
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{ 0x15, 0x3f, 0x15 },
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{ 0x15, 0x3f, 0x3f },
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{ 0x3f, 0x15, 0x15 },
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{ 0x3f, 0x15, 0x3f },
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{ 0x3f, 0x3f, 0x15 },
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{ 0x3f, 0x3f, 0x3f },
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{ 0x39, 0xc, 0x5 },
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{ 0x15, 0x2c, 0xf },
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{ 0x26, 0x10, 0x3d },
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{ 0x29, 0x29, 0x38 },
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{ 0x4, 0x1a, 0xe },
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{ 0x2, 0x1e, 0x3a },
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{ 0x3c, 0x25, 0x33 },
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{ 0x3c, 0xc, 0x2c },
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{ 0x3f, 0x3, 0x2b },
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{ 0x1c, 0x9, 0x13 },
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{ 0x25, 0x2a, 0x35 },
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{ 0x1e, 0xa, 0x38 },
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{ 0x24, 0x8, 0x3 },
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{ 0x3, 0xe, 0x36 },
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{ 0xc, 0x6, 0x2a },
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{ 0x26, 0x3, 0x32 },
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{ 0x5, 0x2f, 0x33 },
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{ 0x3c, 0x35, 0x2f },
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{ 0x2d, 0x26, 0x3e },
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{ 0xd, 0xa, 0x10 },
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{ 0x25, 0x3c, 0x11 },
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{ 0xd, 0x4, 0x2e },
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{ 0x5, 0x19, 0x3e },
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{ 0xc, 0x13, 0x34 },
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{ 0x2b, 0x6, 0x24 },
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{ 0x4, 0x3, 0xd },
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{ 0x2f, 0x3c, 0xc },
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{ 0x2a, 0x37, 0x1f },
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{ 0xf, 0x12, 0x38 },
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{ 0x38, 0xe, 0x2a },
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{ 0x12, 0x2f, 0x19 },
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{ 0x29, 0x2e, 0x31 },
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{ 0x25, 0x13, 0x3e },
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{ 0x33, 0x3e, 0x33 },
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{ 0x1d, 0x2c, 0x25 },
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{ 0x15, 0x15, 0x5 },
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{ 0x32, 0x25, 0x39 },
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{ 0x1a, 0x7, 0x1f },
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{ 0x13, 0xe, 0x1d },
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{ 0x36, 0x17, 0x34 },
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{ 0xf, 0x15, 0x23 },
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{ 0x2, 0x35, 0xd },
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{ 0x15, 0x3f, 0xc },
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{ 0x14, 0x2f, 0xf },
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{ 0x19, 0x21, 0x3e },
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{ 0x27, 0x11, 0x2f },
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{ 0x38, 0x3f, 0x3c },
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{ 0x36, 0x2d, 0x15 },
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{ 0x16, 0x17, 0x2 },
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{ 0x1, 0xa, 0x3d },
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{ 0x1b, 0x11, 0x3f },
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{ 0x21, 0x3c, 0xd },
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{ 0x1a, 0x39, 0x3d },
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{ 0x8, 0xe, 0xe },
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{ 0x22, 0x21, 0x23 },
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{ 0x1e, 0x30, 0x5 },
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{ 0x1f, 0x22, 0x3d },
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{ 0x1e, 0x2f, 0xa },
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{ 0x0, 0x1c, 0xe },
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{ 0x0, 0x1c, 0x15 },
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{ 0x0, 0x1c, 0x1c },
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|
{ 0x0, 0x15, 0x1c },
|
|
|
|
{ 0x0, 0xe, 0x1c },
|
|
|
|
{ 0x0, 0x7, 0x1c },
|
|
|
|
{ 0xe, 0xe, 0x1c },
|
|
|
|
{ 0x11, 0xe, 0x1c },
|
|
|
|
{ 0x15, 0xe, 0x1c },
|
|
|
|
{ 0x18, 0xe, 0x1c },
|
|
|
|
{ 0x1c, 0xe, 0x1c },
|
|
|
|
{ 0x1c, 0xe, 0x18 },
|
|
|
|
{ 0x1c, 0xe, 0x15 },
|
|
|
|
{ 0x1c, 0xe, 0x11 },
|
|
|
|
{ 0x1c, 0xe, 0xe },
|
|
|
|
{ 0x1c, 0x11, 0xe },
|
|
|
|
{ 0x1c, 0x15, 0xe },
|
|
|
|
{ 0x1c, 0x18, 0xe },
|
|
|
|
{ 0x1c, 0x1c, 0xe },
|
|
|
|
{ 0x18, 0x1c, 0xe },
|
|
|
|
{ 0x15, 0x1c, 0xe },
|
|
|
|
{ 0x11, 0x1c, 0xe },
|
|
|
|
{ 0xe, 0x1c, 0xe },
|
|
|
|
{ 0xe, 0x1c, 0x11 },
|
|
|
|
{ 0xe, 0x1c, 0x15 },
|
|
|
|
{ 0xe, 0x1c, 0x18 },
|
|
|
|
{ 0xe, 0x1c, 0x1c },
|
|
|
|
{ 0xe, 0x18, 0x1c },
|
|
|
|
{ 0xe, 0x15, 0x1c },
|
|
|
|
{ 0xe, 0x11, 0x1c },
|
|
|
|
{ 0x14, 0x14, 0x1c },
|
|
|
|
{ 0x16, 0x14, 0x1c },
|
|
|
|
{ 0x18, 0x14, 0x1c },
|
|
|
|
{ 0x1a, 0x14, 0x1c },
|
|
|
|
{ 0x1c, 0x14, 0x1c },
|
|
|
|
{ 0x1c, 0x14, 0x1a },
|
|
|
|
{ 0x1c, 0x14, 0x18 },
|
|
|
|
{ 0x1c, 0x14, 0x16 },
|
|
|
|
{ 0x1c, 0x14, 0x14 },
|
|
|
|
{ 0x1c, 0x16, 0x14 },
|
|
|
|
{ 0x1c, 0x18, 0x14 },
|
|
|
|
{ 0x1c, 0x1a, 0x14 },
|
|
|
|
{ 0x1c, 0x1c, 0x14 },
|
|
|
|
{ 0x1a, 0x1c, 0x14 },
|
|
|
|
{ 0x18, 0x1c, 0x14 },
|
|
|
|
{ 0x16, 0x1c, 0x14 },
|
|
|
|
{ 0x14, 0x1c, 0x14 },
|
|
|
|
{ 0x14, 0x1c, 0x16 },
|
|
|
|
{ 0x14, 0x1c, 0x18 },
|
|
|
|
{ 0x14, 0x1c, 0x1a },
|
|
|
|
{ 0x14, 0x1c, 0x1c },
|
|
|
|
{ 0x14, 0x1a, 0x1c },
|
|
|
|
{ 0x14, 0x18, 0x1c },
|
|
|
|
{ 0x14, 0x16, 0x1c },
|
|
|
|
{ 0x0, 0x0, 0x10 },
|
|
|
|
{ 0x4, 0x0, 0x10 },
|
|
|
|
{ 0x8, 0x0, 0x10 },
|
|
|
|
{ 0xc, 0x0, 0x10 },
|
|
|
|
{ 0x10, 0x0, 0x10 },
|
|
|
|
{ 0x10, 0x0, 0xc },
|
|
|
|
{ 0x10, 0x0, 0x8 },
|
|
|
|
{ 0x10, 0x0, 0x4 },
|
|
|
|
{ 0x10, 0x0, 0x0 },
|
|
|
|
{ 0x10, 0x4, 0x0 },
|
|
|
|
{ 0x10, 0x8, 0x0 },
|
|
|
|
{ 0x10, 0xc, 0x0 },
|
|
|
|
{ 0x10, 0x10, 0x0 },
|
|
|
|
{ 0xc, 0x10, 0x0 },
|
|
|
|
{ 0x8, 0x10, 0x0 },
|
|
|
|
{ 0x4, 0x10, 0x0 },
|
|
|
|
{ 0x0, 0x10, 0x0 },
|
|
|
|
{ 0x0, 0x10, 0x4 },
|
|
|
|
{ 0x0, 0x10, 0x8 },
|
|
|
|
{ 0x0, 0x10, 0xc },
|
|
|
|
{ 0x0, 0x10, 0x10 },
|
|
|
|
{ 0x0, 0xc, 0x10 },
|
|
|
|
{ 0x0, 0x8, 0x10 },
|
|
|
|
{ 0x0, 0x4, 0x10 },
|
|
|
|
{ 0x8, 0x8, 0x10 },
|
|
|
|
{ 0xa, 0x8, 0x10 },
|
|
|
|
{ 0xc, 0x8, 0x10 },
|
|
|
|
{ 0xe, 0x8, 0x10 },
|
|
|
|
{ 0x10, 0x8, 0x10 },
|
|
|
|
{ 0x10, 0x8, 0xe },
|
|
|
|
{ 0x10, 0x8, 0xc },
|
|
|
|
{ 0x10, 0x8, 0xa },
|
|
|
|
{ 0x10, 0x8, 0x8 },
|
|
|
|
{ 0x10, 0xa, 0x8 },
|
|
|
|
{ 0x10, 0xc, 0x8 },
|
|
|
|
{ 0x10, 0xe, 0x8 },
|
|
|
|
{ 0x10, 0x10, 0x8 },
|
|
|
|
{ 0xe, 0x10, 0x8 },
|
|
|
|
{ 0xc, 0x10, 0x8 },
|
|
|
|
{ 0xa, 0x10, 0x8 },
|
|
|
|
{ 0x8, 0x10, 0x8 },
|
|
|
|
{ 0x8, 0x10, 0xa },
|
|
|
|
{ 0x8, 0x10, 0xc },
|
|
|
|
{ 0x8, 0x10, 0xe },
|
|
|
|
{ 0x8, 0x10, 0x10 },
|
|
|
|
{ 0x8, 0xe, 0x10 },
|
|
|
|
{ 0x8, 0xc, 0x10 },
|
|
|
|
{ 0x8, 0xa, 0x10 },
|
|
|
|
{ 0xb, 0xb, 0x10 },
|
|
|
|
{ 0xc, 0xb, 0x10 },
|
|
|
|
{ 0xd, 0xb, 0x10 },
|
|
|
|
{ 0xf, 0xb, 0x10 },
|
|
|
|
{ 0x10, 0xb, 0x10 },
|
|
|
|
{ 0x10, 0xb, 0xf },
|
|
|
|
{ 0x10, 0xb, 0xd },
|
|
|
|
{ 0x10, 0xb, 0xc },
|
|
|
|
{ 0x10, 0xb, 0xb },
|
|
|
|
{ 0x10, 0xc, 0xb },
|
|
|
|
{ 0x10, 0xd, 0xb },
|
|
|
|
{ 0x10, 0xf, 0xb },
|
|
|
|
{ 0x10, 0x10, 0xb },
|
|
|
|
{ 0xf, 0x10, 0xb },
|
|
|
|
{ 0xd, 0x10, 0xb },
|
|
|
|
{ 0xc, 0x10, 0xb },
|
|
|
|
{ 0xb, 0x10, 0xb },
|
|
|
|
{ 0xb, 0x10, 0xc },
|
|
|
|
{ 0xb, 0x10, 0xd },
|
|
|
|
{ 0xb, 0x10, 0xf },
|
|
|
|
{ 0xb, 0x10, 0x10 },
|
|
|
|
{ 0xb, 0xf, 0x10 },
|
|
|
|
{ 0xb, 0xd, 0x10 },
|
|
|
|
{ 0xb, 0xc, 0x10 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
|
|
|
{ 0x0, 0x0, 0x0 },
|
1998-01-16 07:17:36 +03:00
|
|
|
};
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
u_char AC[21] = {
|
|
|
|
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
|
|
|
|
0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
|
|
|
|
0x0C, 0x00, 0x0F, 0x08, 0x00
|
|
|
|
};
|
1998-01-16 07:17:36 +03:00
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
void enablePCIvideo __P((int));
|
|
|
|
static int scanPCI __P((void));
|
|
|
|
static int PCIVendor __P((int));
|
|
|
|
int delayLoop __P((int));
|
|
|
|
void setTextRegs __P((struct VgaRegs *));
|
|
|
|
void setTextCLUT __P((void));
|
|
|
|
void loadFont __P((u_char *));
|
|
|
|
void unlockS3 __P((void));
|
|
|
|
#ifdef DEBUG
|
|
|
|
static void printslots __P((void));
|
|
|
|
#endif
|
1998-01-16 07:17:36 +03:00
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
static inline void
|
|
|
|
outw(port, val)
|
|
|
|
int port;
|
|
|
|
u_short val;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
outb(port, val >> 8);
|
|
|
|
outb(port+1, val);
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
|
|
|
vga_reset(ISA_mem)
|
|
|
|
u_char *ISA_mem;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
int slot;
|
|
|
|
struct VgaRegs *VgaTextRegs;
|
|
|
|
|
|
|
|
/* See if VGA already in TEXT mode - exit if so! */
|
|
|
|
outb(0x3CE, 0x06);
|
|
|
|
if ((inb(0x3CF) & 0x01) == 0) return;
|
|
|
|
|
|
|
|
/* If no VGA responding in text mode, then we have some work to do... */
|
|
|
|
slot = scanPCI(); /* find video card in use */
|
|
|
|
enablePCIvideo(slot); /* enable I/O to card */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Note: the PCI scanning code does not yet work correctly
|
|
|
|
* for non-Moto boxes, so the switch below only
|
|
|
|
* defaults to using an S3 card if it does not
|
|
|
|
* find a Cirrus card.
|
|
|
|
*
|
|
|
|
* The only reason we need to scan the bus looking for
|
|
|
|
* a graphics card is so we could do the "enablePCIvideo(slot)"
|
|
|
|
* call above; it is needed because Moto's OpenFirmware
|
|
|
|
* disables I/O to the graphics adapter before it gives
|
|
|
|
* us control. PEK'97
|
|
|
|
*/
|
|
|
|
|
|
|
|
switch (PCIVendor(slot)) {
|
|
|
|
default: /* Assume S3 */
|
|
|
|
/* case(S3Vendor): */
|
|
|
|
unlockS3();
|
|
|
|
VgaTextRegs = S3TextRegs;
|
|
|
|
outw(0x3C4, 0x0120); /* disable video */
|
|
|
|
setTextRegs(VgaTextRegs); /* initial register setup */
|
|
|
|
setTextCLUT(); /* load color lookup table */
|
|
|
|
loadFont(ISA_mem); /* load font */
|
|
|
|
setTextRegs(VgaTextRegs); /* reload registers */
|
|
|
|
outw(0x3C4, 0x0100); /* re-enable video */
|
|
|
|
outb(0x3c2, 0x63); /* MISC */
|
|
|
|
outb(0x3c2, 0x67); /* MISC */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case(CirrusVendor):
|
|
|
|
VgaTextRegs = GenVgaTextRegs;
|
|
|
|
outw(0x3C4, 0x0612); /* unlock ext regs */
|
|
|
|
outw(0x3C4, 0x0700); /* reset ext sequence mode */
|
|
|
|
outw(0x3C4, 0x0120); /* disable video */
|
|
|
|
setTextRegs(VgaTextRegs); /* initial register setup */
|
|
|
|
setTextCLUT(); /* load color lookup table */
|
|
|
|
loadFont(ISA_mem); /* load font */
|
|
|
|
setTextRegs(VgaTextRegs); /* reload registers */
|
|
|
|
outw(0x3C4, 0x0100); /* re-enable video */
|
|
|
|
outb(0x3c2, 0x63); /* MISC */
|
|
|
|
break;
|
|
|
|
|
|
|
|
case (DiamondVendor):
|
|
|
|
case (MatroxVendor):
|
|
|
|
/*
|
|
|
|
* The following code is almost enuf to get the Matrox
|
|
|
|
* working (on a Moto box) but the video is not stable.
|
|
|
|
* We probably need to tweak the TVP3026 Video PLL regs. PEK'97
|
|
|
|
*/
|
1999-06-28 05:20:43 +04:00
|
|
|
VgaTextRegs = GenVgaTextRegs;
|
1998-01-16 07:17:36 +03:00
|
|
|
outw(0x3C4, 0x0120); /* disable video */
|
|
|
|
setTextRegs(VgaTextRegs); /* initial register setup */
|
|
|
|
setTextCLUT(); /* load color lookup table */
|
|
|
|
loadFont(ISA_mem); /* load font */
|
|
|
|
setTextRegs(VgaTextRegs); /* reload registers */
|
|
|
|
outw(0x3C4, 0x0100); /* re-enable video */
|
|
|
|
outb(0x3c2, 0x63); /* MISC */
|
1999-06-28 05:20:43 +04:00
|
|
|
printf("VGA Chip Vendor ID: 0x%08x\n", PCIVendor(slot));
|
1998-01-16 07:17:36 +03:00
|
|
|
delayLoop(1);
|
|
|
|
break;
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef DEBUG
|
|
|
|
printslots();
|
|
|
|
delayLoop(5);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
delayLoop(2); /* give time for the video monitor to come up */
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Write to VGA Attribute registers.
|
|
|
|
*/
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
1998-01-16 07:17:36 +03:00
|
|
|
writeAttr(index, data, videoOn)
|
1999-06-28 05:20:43 +04:00
|
|
|
u_char index;
|
|
|
|
u_char data;
|
|
|
|
u_char videoOn; /* video on flag */
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
1999-06-28 05:20:43 +04:00
|
|
|
u_char v;
|
1998-01-16 07:17:36 +03:00
|
|
|
v = inb(0x3da); /* reset attr. address toggle */
|
|
|
|
if (videoOn)
|
|
|
|
outb(0x3c0, (index & 0x1F) | 0x20);
|
|
|
|
else
|
|
|
|
outb(0x3c0, (index & 0x1F));
|
|
|
|
outb(0x3c0, data);
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
|
|
|
setTextRegs(svp)
|
|
|
|
struct VgaRegs *svp;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* saved settings
|
|
|
|
*/
|
1999-06-28 05:20:43 +04:00
|
|
|
while (svp->io_port != ENDMK) {
|
1998-01-16 07:17:36 +03:00
|
|
|
outb(svp->io_port, svp->io_index);
|
|
|
|
outb(svp->io_port+1, svp->io_value);
|
|
|
|
svp++;
|
|
|
|
}
|
|
|
|
|
|
|
|
outb(0x3c2, 0x67); /* MISC */
|
|
|
|
outb(0x3c6, 0xff); /* MASK */
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
for (i = 0; i < 0x10; i++)
|
1998-01-16 07:17:36 +03:00
|
|
|
writeAttr(i, AC[i], 0); /* pallete */
|
|
|
|
writeAttr(0x10, 0x0c, 0); /* text mode */
|
|
|
|
writeAttr(0x11, 0x00, 0); /* overscan color (border) */
|
|
|
|
writeAttr(0x12, 0x0f, 0); /* plane enable */
|
|
|
|
writeAttr(0x13, 0x08, 0); /* pixel panning */
|
|
|
|
writeAttr(0x14, 0x00, 1); /* color select; video on */
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
1998-01-16 07:17:36 +03:00
|
|
|
setTextCLUT()
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
outb(0x3C6, 0xFF);
|
|
|
|
i = inb(0x3C7);
|
|
|
|
outb(0x3C8, 0);
|
|
|
|
i = inb(0x3C7);
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
for (i = 0; i < 256; i++) {
|
1998-01-16 07:17:36 +03:00
|
|
|
outb(0x3C9, TextCLUT[i].r);
|
|
|
|
outb(0x3C9, TextCLUT[i].g);
|
|
|
|
outb(0x3C9, TextCLUT[i].b);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
|
|
|
loadFont(ISA_mem)
|
|
|
|
u_char *ISA_mem;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
int i, j;
|
1999-06-28 05:20:43 +04:00
|
|
|
u_char *font_page = (u_char *)&ISA_mem[0xA0000];
|
1998-01-16 07:17:36 +03:00
|
|
|
|
|
|
|
outb(0x3C2, 0x67);
|
|
|
|
/*
|
|
|
|
* Load font
|
|
|
|
*/
|
|
|
|
i = inb(0x3DA); /* Reset Attr toggle */
|
|
|
|
|
|
|
|
outb(0x3C0,0x30);
|
|
|
|
outb(0x3C0, 0x01); /* graphics mode */
|
|
|
|
|
|
|
|
outw(0x3C4, 0x0001); /* reset sequencer */
|
|
|
|
outw(0x3C4, 0x0204); /* write to plane 2 */
|
|
|
|
outw(0x3C4, 0x0406); /* enable plane graphics */
|
|
|
|
outw(0x3C4, 0x0003); /* reset sequencer */
|
|
|
|
outw(0x3CE, 0x0402); /* read plane 2 */
|
|
|
|
outw(0x3CE, 0x0500); /* write mode 0, read mode 0 */
|
|
|
|
outw(0x3CE, 0x0605); /* set graphics mode */
|
|
|
|
|
|
|
|
for (i = 0; i < sizeof(font); i += 16) {
|
|
|
|
for (j = 0; j < 16; j++) {
|
|
|
|
__asm__ volatile("eieio");
|
|
|
|
font_page[(2*i)+j] = font[i+j];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
unlockS3()
|
|
|
|
{
|
|
|
|
/* From the S3 manual */
|
|
|
|
outb(0x46E8, 0x10); /* Put into setup mode */
|
|
|
|
outb(0x3C3, 0x10);
|
|
|
|
outb(0x102, 0x01); /* Enable registers */
|
|
|
|
outb(0x46E8, 0x08); /* Enable video */
|
|
|
|
outb(0x3C3, 0x08);
|
|
|
|
outb(0x4AE8, 0x00);
|
|
|
|
|
|
|
|
outb(0x42E8, 0x80); /* Reset graphics engine? */
|
|
|
|
|
|
|
|
outb(0x3D4, 0x38); /* Unlock all registers */
|
|
|
|
outb(0x3D5, 0x48);
|
|
|
|
outb(0x3D4, 0x39);
|
|
|
|
outb(0x3D5, 0xA5);
|
|
|
|
outb(0x3D4, 0x40);
|
|
|
|
outb(0x3D5, inb(0x3D5)|0x01);
|
|
|
|
outb(0x3D4, 0x33);
|
|
|
|
outb(0x3D5, inb(0x3D5)&~0x52);
|
|
|
|
outb(0x3D4, 0x35);
|
|
|
|
outb(0x3D5, inb(0x3D5)&~0x30);
|
|
|
|
outb(0x3D4, 0x3A);
|
|
|
|
outb(0x3D5, 0x00);
|
|
|
|
outb(0x3D4, 0x53);
|
|
|
|
outb(0x3D5, 0x00);
|
|
|
|
outb(0x3D4, 0x31);
|
|
|
|
outb(0x3D5, inb(0x3D5)&~0x4B);
|
|
|
|
outb(0x3D4, 0x58);
|
|
|
|
|
|
|
|
outb(0x3D5, 0);
|
|
|
|
|
|
|
|
outb(0x3D4, 0x54);
|
|
|
|
outb(0x3D5, 0x38);
|
|
|
|
outb(0x3D4, 0x60);
|
|
|
|
outb(0x3D5, 0x07);
|
|
|
|
outb(0x3D4, 0x61);
|
|
|
|
outb(0x3D5, 0x80);
|
|
|
|
outb(0x3D4, 0x62);
|
|
|
|
outb(0x3D5, 0xA1);
|
|
|
|
outb(0x3D4, 0x69); /* High order bits for cursor address */
|
|
|
|
outb(0x3D5, 0);
|
|
|
|
|
|
|
|
outb(0x3D4, 0x32);
|
|
|
|
outb(0x3D5, inb(0x3D5)&~0x10);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ============ */
|
|
|
|
|
|
|
|
|
|
|
|
#define NSLOTS 4
|
|
|
|
#define NPCIREGS 5
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
/*
|
1998-01-16 07:17:36 +03:00
|
|
|
* should use devfunc number/indirect method to be totally safe on
|
1999-06-28 05:20:43 +04:00
|
|
|
* all machines, this works for now on 3 slot Moto boxes
|
1998-01-16 07:17:36 +03:00
|
|
|
*/
|
|
|
|
|
|
|
|
struct PCI_ConfigInfo {
|
1999-06-28 05:20:43 +04:00
|
|
|
u_long * config_addr;
|
|
|
|
u_long regs[NPCIREGS];
|
1998-01-16 07:17:36 +03:00
|
|
|
} PCI_slots [NSLOTS] = {
|
1999-06-28 05:20:43 +04:00
|
|
|
{ (u_long *)0x80802000, { 0xDE, 0xAD, 0xBE, 0xEF } },
|
|
|
|
{ (u_long *)0x80804000, { 0xDE, 0xAD, 0xBE, 0xEF } },
|
|
|
|
{ (u_long *)0x80808000, { 0xDE, 0xAD, 0xBE, 0xEF } },
|
|
|
|
{ (u_long *)0x80810000, { 0xDE, 0xAD, 0xBE, 0xEF } }
|
1998-01-16 07:17:36 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The following code modifies the PCI Command register
|
|
|
|
* to enable memory and I/O accesses.
|
|
|
|
*/
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
1998-01-16 07:17:36 +03:00
|
|
|
enablePCIvideo(slot)
|
1999-06-28 05:20:43 +04:00
|
|
|
int slot;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
1999-06-28 05:20:43 +04:00
|
|
|
volatile u_char * ppci;
|
1998-01-16 07:17:36 +03:00
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
ppci = (u_char *)PCI_slots[slot].config_addr;
|
1998-01-16 07:17:36 +03:00
|
|
|
ppci[4] = 0x0003; /* enable memory and I/O accesses */
|
|
|
|
__asm__ volatile("eieio");
|
|
|
|
|
|
|
|
outb(0x3d4, 0x11);
|
|
|
|
outb(0x3d5, 0x0e); /* unlock CR0-CR7 */
|
|
|
|
}
|
|
|
|
|
|
|
|
#define DEVID 0
|
|
|
|
#define CMD 1
|
|
|
|
#define CLASS 2
|
|
|
|
#define MEMBASE 4
|
|
|
|
|
|
|
|
int
|
1999-06-28 05:20:43 +04:00
|
|
|
scanPCI()
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
int slt, r;
|
|
|
|
struct PCI_ConfigInfo *pslot;
|
|
|
|
int theSlot = -1;
|
|
|
|
int highVgaSlot = -1;
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
for (slt = 0; slt < NSLOTS; slt++) {
|
1998-01-16 07:17:36 +03:00
|
|
|
pslot = &PCI_slots[slt];
|
1999-06-28 05:20:43 +04:00
|
|
|
for (r = 0; r < NPCIREGS; r++) {
|
1998-10-26 03:45:47 +03:00
|
|
|
pslot->regs[r] = bswap32(pslot->config_addr[r]);
|
1998-01-16 07:17:36 +03:00
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
if (pslot->regs[DEVID] != 0xFFFFFFFF) { /* card in slot ? */
|
|
|
|
if ((pslot->regs[CLASS] & 0xFFFFFF00) == 0x03000000) { /* VGA ? */
|
1998-01-16 07:17:36 +03:00
|
|
|
highVgaSlot = slt;
|
1999-06-28 05:20:43 +04:00
|
|
|
if ((pslot->regs[CMD] & 0x03)) { /* did firmware enable it ? */
|
1998-01-16 07:17:36 +03:00
|
|
|
theSlot = slt;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
if (theSlot == -1)
|
1998-01-16 07:17:36 +03:00
|
|
|
theSlot = highVgaSlot;
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
return (theSlot);
|
1998-01-16 07:17:36 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
int
|
1999-06-28 05:20:43 +04:00
|
|
|
delayLoop(k)
|
|
|
|
int k;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
volatile int a, b;
|
|
|
|
volatile int i, j;
|
|
|
|
a = 0;
|
|
|
|
do {
|
1999-06-28 05:20:43 +04:00
|
|
|
for (i = 0; i < 500; i++) {
|
1998-01-16 07:17:36 +03:00
|
|
|
b = i;
|
1999-06-28 05:20:43 +04:00
|
|
|
for (j = 0; j < 200; j++) {
|
1998-01-16 07:17:36 +03:00
|
|
|
a = b+j;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} while (k--);
|
|
|
|
return(a);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* return Vendor ID of card in the slot */
|
|
|
|
static
|
1999-06-28 05:20:43 +04:00
|
|
|
int PCIVendor(slotnum)
|
|
|
|
int slotnum;
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
struct PCI_ConfigInfo *pslot;
|
|
|
|
|
|
|
|
pslot = &PCI_slots[slotnum];
|
|
|
|
|
|
|
|
return (pslot->regs[DEVID] & 0xFFFF);
|
|
|
|
}
|
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
#ifdef DEBUG
|
1998-01-16 07:17:36 +03:00
|
|
|
static
|
1999-06-28 05:20:43 +04:00
|
|
|
void
|
|
|
|
printslots()
|
1998-01-16 07:17:36 +03:00
|
|
|
{
|
|
|
|
int i;
|
1999-06-28 05:20:43 +04:00
|
|
|
for (i = 0; i < NSLOTS; i++) {
|
1998-01-16 07:17:36 +03:00
|
|
|
|
1999-06-28 05:20:43 +04:00
|
|
|
printf("PCI Slot number: %d", i);
|
|
|
|
printf(" Vendor ID: 0x%08x\n", PCIVendor(i));
|
1998-01-16 07:17:36 +03:00
|
|
|
}
|
|
|
|
}
|
1999-06-28 05:20:43 +04:00
|
|
|
#endif /* DEBUG */
|
1998-01-16 07:17:36 +03:00
|
|
|
#endif /* CONS_VGA */
|