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NetBSD/sys/arch/mips/include/mips1_pte.h

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Merge the ppcoea-renovation branch to HEAD. This branch was a major cleanup and rototill of many of the various OEA cpu based PPC ports that focused on sharing as much code as possible between the various ports to eliminate near-identical copies of files in every tree. Additionally there is a new PIC system that unifies the interface to interrupt code for all different OEA ppc arches. The work for this branch was done by a variety of people, too long to list here. TODO: bebox still needs work to complete the transition to -renovation. ofppc still needs a bunch of work, which I will be looking at. ev64260 still needs to be renovated amigappc was not attempted. NOTES: pmppc was removed as an arch, and moved to a evbppc target.
2007-10-17 23:52:51 +04:00
/* $NetBSD: mips1_pte.h,v 1.17 2007/10/17 19:55:37 garbled Exp $ */
new RCS ID format.
1994-10-27 00:08:38 +03:00
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
/*
upgrade to bsd 4.4-lite code base. only mod is rcsids
1994-05-27 12:40:50 +04:00
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
Move UCB-licensed code from 4-clause to 3-clause licence. Patches provided by Joel Baker in PR 22364, verified by myself.
2003-08-07 20:26:28 +04:00
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: pte.h 1.11 89/09/03
*
* @(#)pte.h 8.1 (Berkeley) 6/10/93
*/
/*
* Copyright (c) 1988 University of Utah.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department and Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah Hdr: pte.h 1.11 89/09/03
upgrade to bsd 4.4-lite code base. only mod is rcsids
1994-05-27 12:40:50 +04:00
*
new RCS ID format.
1994-10-27 00:08:38 +03:00
* @(#)pte.h 8.1 (Berkeley) 6/10/93
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
*/
/*
* R2000 hardware page table entry
*/
LOCORE -> _LOCORE
1996-02-02 01:28:24 +03:00
#ifndef _LOCORE
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
struct mips1_pte {
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
#if BYTE_ORDER == BIG_ENDIAN
unsigned int pg_pfnum:20, /* HW: core page frame number or 0 */
pg_n:1, /* HW: non-cacheable bit */
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'. There is a growing concern of misuse in NetBSD/mips.
1999-05-27 05:56:32 +04:00
pg_m:1, /* HW: dirty bit */
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
pg_v:1, /* HW: valid bit */
pg_g:1, /* HW: ignore pid bit */
:4,
pg_swapm:1, /* SW: page must be forced to swap */
pg_fod:1, /* SW: is fill on demand (=0) */
pg_prot:2; /* SW: access control */
#endif
#if BYTE_ORDER == LITTLE_ENDIAN
unsigned int pg_prot:2, /* SW: access control */
pg_fod:1, /* SW: is fill on demand (=0) */
pg_swapm:1, /* SW: page must be forced to swap */
:4,
pg_g:1, /* HW: ignore pid bit */
pg_v:1, /* HW: valid bit */
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'. There is a growing concern of misuse in NetBSD/mips.
1999-05-27 05:56:32 +04:00
pg_m:1, /* HW: dirty bit */
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
pg_n:1, /* HW: non-cacheable bit */
pg_pfnum:20; /* HW: core page frame number or 0 */
#endif
};
LOCORE -> _LOCORE
1996-02-02 01:28:24 +03:00
#endif /* _LOCORE */
pmax code from <ralphc@pyramid.com> & <rick@snowhite.cis.uoguelph.ca>
1993-10-12 06:22:19 +03:00
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS1_PG_PROT 0x00000003
#define MIPS1_PG_RW 0x00000000
#define MIPS1_PG_RO 0x00000001
#define MIPS1_PG_WIRED 0x00000002
#define MIPS1_PG_G 0x00000100
#define MIPS1_PG_V 0x00000200
#define MIPS1_PG_NV 0x00000000
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'. There is a growing concern of misuse in NetBSD/mips.
1999-05-27 05:56:32 +04:00
#define MIPS1_PG_D 0x00000400
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS1_PG_N 0x00000800
#define MIPS1_PG_FRAME 0xfffff000
#define MIPS1_PG_SHIFT 12
#define MIPS1_PG_PFNUM(x) (((x) & MIPS1_PG_FRAME) >> MIPS1_PG_SHIFT)
More merged MIPS1/MIPS3 support. The pte definitions still need work before they can be support both MIPS1 and MIPS3.
1997-06-15 21:24:22 +04:00
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'. There is a growing concern of misuse in NetBSD/mips.
1999-05-27 05:56:32 +04:00
#define MIPS1_PG_ROPAGE MIPS1_PG_V
#define MIPS1_PG_RWPAGE MIPS1_PG_D
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS1_PG_CWPAGE 0
add definitions for non-cached pages
2007-07-17 07:53:56 +04:00
#define MIPS1_PG_RWNCPAGE (MIPS1_PG_D | MIPS1_PG_N)
#define MIPS1_PG_CWNCPAGE MIPS1_PG_N
- Change a symbolic name of TLB entrylo from 'PG_M' to 'PG_D' to reflect processor design. MIPS 'dirty bit' is not the same as i386 'dirty bit'. There is a growing concern of misuse in NetBSD/mips.
1999-05-27 05:56:32 +04:00
#define MIPS1_PG_IOPAGE (MIPS1_PG_D | MIPS1_PG_N)
More merged MIPS1/MIPS3 support. The pte definitions still need work before they can be support both MIPS1 and MIPS3.
1997-06-15 21:24:22 +04:00
rename vad_to_pfn() -> mips_paddr_to_tlbpfn() pfn_to_vad() -> mips_tlbpfn_to_paddr() as suggested by thorpej on port-mips Mar 27.
2000-06-09 09:51:42 +04:00
#define mips1_tlbpfn_to_paddr(x) ((x) & MIPS1_PG_FRAME)
#define mips1_paddr_to_tlbpfn(x) (x)
More merged MIPS1/MIPS3 support. The pte definitions still need work before they can be support both MIPS1 and MIPS3.
1997-06-15 21:24:22 +04:00
Changes for configuring both MIPS1 and MIPS3, from a merge of similar design and code by Jason Thorpe and Jonathan Stone. NOTE: the kernel-stack-switching code and cacheflush() calls in locore.S still use #ifdef MIPS3 and need more work. mips/include/cpu.h: Add CPUISMIPS3 for run-time tests of what CPU architecture level we're running on. mips/include/locore.h: Add declarations of locore cache-size variables for ref/def toolchain. mips/include/mips1_pte.h: mips1 TLB bit definitions. mips/include/mips3_pte.h: mips3 TLB bit definitions. mips/include/pte.h: define accesor macros for TLB bits (e.g., mips_pg_m_bit(), that expand to CPU constants if only one CPU arch is configured, or to inline functions if both MIPS1 and MIPS3 are configured. mips/mips/locore_r2000.S: Use MIPS1_PG_xxx constants inside mips1-specific code. mips/mips/locore_r4000.S: Use MIPS3_PG_xxx constants inside mips3-specific code. mips/mips/locore.S: Use MIPS1_PG_xxx constants inside mips3-specific code. Use MIPS1_PG_xxx constants inside mips1-specific code. (Needs more work!) mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c: Use MIPS3_PG_xxx constants inside mips3-specific functions, and MIPS1_PG_XXX inside mips1-specific code. Otherwise, use mips_pg_XXX_bit() macros where they apply, and use "if (CPUISMIPS3) { ... } else {... }" where they don't. mips/mips/mips_machdep.c: Import Michael Hitch's fixes from the pmax locore-init code into mips_vector_init(). pmax/pmax/machdep.c: Use generic mips_vector_init() locore vector-init function.
1997-06-17 03:41:40 +04:00
#define MIPS1_PTE_TO_PADDR(pte) ((unsigned)(pte) & MIPS1_PG_FRAME)
make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT.
2000-06-09 08:36:43 +04:00
#define MIPS1_PAGE_IS_RDONLY(pte,va) ((int)(pte) & MIPS1_PG_RO)