92 lines
4.0 KiB
C
92 lines
4.0 KiB
C
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/* $NetBSD: rtcreg.h,v 1.1 2002/07/05 13:31:54 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_RTCREG_H
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#define _SH5_RTCREG_H
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/*
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* Register Offsets for the RTC module
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*/
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#define RTC_REG_R64CNT 0x00 /* Frequency Divider Counter */
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#define RTC_R64CNT_MASK 0x7f
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#define RTC_REG_RSECCNT 0x04 /* Second Counter */
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#define RTC_REG_RMINCNT 0x08 /* Minute Counter */
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#define RTC_REG_RHRCNT 0x0c /* Hour Counter */
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#define RTC_REG_RWKCNT 0x10 /* Day-of-week Counter */
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#define RTC_REG_RDAYCNT 0x14 /* Day Counter */
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#define RTC_REG_RMONCNT 0x18 /* Month Counter */
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#define RTC_REG_RYRCNT 0x1c /* Year Counter */
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#define RTC_REG_RSECAR 0x20 /* Second Alarm Register */
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#define RTC_REG_RMINAR 0x24 /* Minute Alarm Register */
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#define RTC_REG_RHRAR 0x28 /* Hour Alarm Register */
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#define RTC_REG_RWKAR 0x2c /* Week Alarm Register */
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#define RTC_REG_RDAYAR 0x30 /* Day Alarm Register */
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#define RTC_REG_RMONAR 0x34 /* Month Alarm Register */
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#define RTC_REG_RCR1 0x38 /* RTC Control Register #1 */
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#define RTC_REG_RCR2 0x3c /* RTC Control Register #2 */
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#define RTC_REG_SIZE 0x40
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/*
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* Bits in Control Register #1
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*/
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#define RTC_RCR1_AF 0x01 /* Alarm Flag */
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#define RTC_RCR1_AIE 0x08 /* Alarm Interrupt Enable Flag */
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#define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable Flag */
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#define RTC_RCR1_CF 0x80 /* Carry Flag */
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/*
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* Bits in Control Register #2
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*/
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#define RTC_RCR2_START 0x01 /* Start Bit */
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#define RTC_RCR2_RESET 0x02 /* Reset Bit */
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#define RTC_RCR2_ADJ 0x04 /* Second Adjustment */
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#define RTC_RCR2_RTCEN 0x08 /* Oscillator Enable */
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#define RTC_RCR2_PSEN_MASK 0x70 /* Periodic Interrupt Enable */
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#define RTC_RCR2_PSEN_NONE 0x00 /* No Periodic Interrupt Generation */
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#define RTC_RCR2_PSEN_256 0x10 /* Interrupt at 1/256 second interval */
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#define RTC_RCR2_PSEN_64 0x20 /* Interrupt at 1/64 second interval */
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#define RTC_RCR2_PSEN_16 0x30 /* Interrupt at 1/16 second interval */
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#define RTC_RCR2_PSEN_4 0x40 /* Interrupt at 1/4 second interval */
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#define RTC_RCR2_PSEN_2 0x50 /* Interrupt at 1/2 second interval */
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#define RTC_RCR2_PSEN_1 0x60 /* Interrupt at 1 second interval */
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#define RTC_RCR2_PSEN_2S 0x70 /* Interrupt at 2 second interval */
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#define RTC_RCR2_PEF 0x80 /* Periodic Interrupt Flag */
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#endif /* _SH5_RTCREG_H */
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