2001-11-18 00:26:12 +03:00
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/* $NetBSD: ihareg.h,v 1.3 2001/11/17 21:26:12 tsutsui Exp $ */
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2001-06-03 17:43:45 +04:00
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/*
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* Initio INI-9xxxU/UW SCSI Device Driver
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*
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* Copyright (c) 2000 Ken Westerback
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*-------------------------------------------------------------------------
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*
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* Ported from i91uscsi.h, provided by Initio Corporation, which probably
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* came from the same people who provided i91u.c:
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*
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2001-07-27 20:16:34 +04:00
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* Device driver for the INI-9XXXU/UW or INIC-940/950 PCI SCSI Controller.
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2001-06-03 17:43:45 +04:00
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*
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* FreeBSD
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*
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* Written for 386bsd and FreeBSD by
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* Winston Hung <winstonh@initio.com>
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*
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* Copyright (c) 1997-99 Initio Corp. All rights reserved.
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*
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*-------------------------------------------------------------------------
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*/
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/*
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* Ported to NetBSD by Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> from OpenBSD:
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* $OpenBSD: iha.h,v 1.2 2001/02/08 17:35:05 krw Exp $
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*/
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/*
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2001-07-27 20:16:34 +04:00
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* Tulip (aka inic-940/950) PCI Configuration Space Initio Specific Registers
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2001-06-03 17:43:45 +04:00
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*
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* Offsets 0x00 through 0x3f are the standard PCI Configuration Header
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* registers.
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*
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* Offsets 0x40 through 0x4f, 0x51, 0x53, 0x57, 0x5b, 0x5e and 0x5f are
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* reserved registers.
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*
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* Registers 0x50 and 0x52 always read as 0.
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*
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* The register offset names and associated bit field names are taken
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2001-07-27 20:16:34 +04:00
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* from the Inic-950 Data Sheet, Version 2.1, March 1997
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2001-06-03 17:43:45 +04:00
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*/
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#define TUL_GCTRL0 0x54 /* R/W Global Control 0 */
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#define EEPRG 0x04 /* Enable EEPROM Programming */
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#define TUL_GCTRL1 0x55 /* R/W Global Control 1 */
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#define ATDEN 0x01 /* Auto Termination Detect Enable */
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#define TUL_GSTAT 0x56 /* R/W Global Status - connector type */
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#define TUL_EPAD0 0x58 /* R/W External EEPROM Addr (lo byte) */
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#define TUL_EPAD1 0x59 /* R/W External EEPROM Addr (hi byte) */
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#define TUL_PNVPG 0x5A /* R/W Data port to external BIOS */
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#define TUL_EPDATA 0x5C /* R/W EEPROM Data port */
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#define TUL_NVRAM 0x5D /* R/W Non-volatile RAM port */
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#define READ 0x80 /* Read from given NVRAM addr */
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#define WRITE 0x40 /* Write to given NVRAM addr */
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#define ENABLE_ERASE 0x30 /* Enable NVRAM Erase/Write */
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#define NVRCS 0x08 /* Select external NVRAM */
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#define NVRCK 0x04 /* NVRAM Clock */
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#define NVRDO 0x02 /* NVRAM Write Data */
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#define NVRDI 0x01 /* NVRAM Read Data */
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/*
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2001-07-27 20:16:34 +04:00
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* Tulip (aka inic-940/950) SCSI Registers
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2001-06-03 17:43:45 +04:00
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*/
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#define TUL_STCNT0 0x80 /* R/W 24 bit SCSI Xfer Count */
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#define TCNT 0x00ffffff /* SCSI Xfer Transfer Count */
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#define TUL_SFIFOCNT 0x83 /* R/W 5 bit FIFO counter */
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#define FIFOC 0x1f /* SCSI Offset Fifo Count */
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#define TUL_SISTAT 0x84 /* R Interrupt Register */
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#define RSELED 0x80 /* Reselected */
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#define STIMEO 0x40 /* Selected/Reselected Timeout */
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#define SBSRV 0x20 /* SCSI Bus Service */
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#define SRSTD 0x10 /* SCSI Reset Detected */
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#define DISCD 0x08 /* Disconnected Status */
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#define SELED 0x04 /* Select Interrupt */
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#define SCAMSCT 0x02 /* SCAM selected */
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#define SCMDN 0x01 /* Command Complete */
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#define TUL_SIEN 0x84 /* W Interrupt enable */
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#define ALL_INTERRUPTS 0xff
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#define TUL_STAT0 0x85 /* R Status 0 */
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#define INTPD 0x80 /* Interrupt pending */
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#define SQACT 0x40 /* Sequencer active */
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#define XFCZ 0x20 /* Xfer counter zero */
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#define SFEMP 0x10 /* FIFO empty */
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#define SPERR 0x08 /* SCSI parity error */
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#define PH_MASK 0x07 /* SCSI phase mask */
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#define TUL_SCTRL0 0x85 /* W Control 0 */
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#define RSSQC 0x20 /* Reset sequence counter */
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#define RSFIFO 0x10 /* Flush FIFO */
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#define CMDAB 0x04 /* Abort command (sequence) */
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#define RSMOD 0x02 /* Reset SCSI Chip */
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#define RSCSI 0x01 /* Reset SCSI Bus */
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#define TUL_STAT1 0x86 /* R Status 1 */
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#define STRCV 0x80 /* Status received */
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#define MSGST 0x40 /* Message sent */
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#define CPDNE 0x20 /* Data phase done */
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#define DPHDN 0x10 /* Data phase done */
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#define STSNT 0x08 /* Status sent */
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#define SXCMP 0x04 /* Xfer completed */
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#define SLCMP 0x02 /* Selection completed */
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#define ARBCMP 0x01 /* Arbitration completed */
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#define TUL_SCTRL1 0x86 /* W Control 1 */
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#define ENSCAM 0x80 /* Enable SCAM */
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#define NIDARB 0x40 /* No ID for Arbitration */
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#define ENLRS 0x20 /* Low Level Reselect */
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#define PWDN 0x10 /* Power down mode */
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#define WCPU 0x08 /* Wide CPU */
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#define EHRSL 0x04 /* Enable HW reselect */
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#define ESBUSOUT 0x02 /* Enable SCSI data bus out latch */
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#define ESBUSIN 0x01 /* Enable SCSI data bus in latch */
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#define TUL_SSTATUS2 0x87 /* R Status 2 */
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#define SABRT 0x80 /* Command aborted */
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#define OSCZ 0x40 /* Offset counter zero */
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#define SFFUL 0x20 /* FIFO full */
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#define TMCZ 0x10 /* Timeout counter zero */
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#define BSYGN 0x08 /* Busy release */
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#define PHMIS 0x04 /* Phase mismatch */
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#define SBEN 0x02 /* SCSI data bus enable */
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#define SRST 0x01 /* SCSI bus reset in progress */
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#define TUL_SCONFIG0 0x87 /* W Configuration */
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#define PHLAT 0x80 /* Enable phase latch */
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#define ITMOD 0x40 /* Initiator mode */
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#define SPCHK 0x20 /* Enable SCSI parity */
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#define ADMA8 0x10 /* Alternate dma 8-bits mode */
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#define ADMAW 0x08 /* Alternate dma 16-bits mode */
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#define EDACK 0x04 /* Enable DACK in wide SCSI xfer */
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#define ALTPD 0x02 /* Alternate sync period mode */
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#define DSRST 0x01 /* Disable SCSI Reset signal */
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#define SCONFIG0DEFAULT (PHLAT | ITMOD | ALTPD | DSRST)
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#define TUL_SOFSC 0x88 /* R Offset */
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#define PERIOD_WIDE_SCSI 0x80 /* Enable Wide SCSI */
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#define PERIOD_SYXPD 0x70 /* Synch. SCSI Xfer rate */
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#define PERIOD_SYOFS 0x0f /* Synch. SCSI Offset */
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#define TUL_SYNCM 0x88 /* W Sync. Xfer Period & Offset */
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#define TUL_SBID 0x89 /* R SCSI BUS ID */
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#define TUL_SID 0x89 /* W SCSI ID */
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#define TUL_SALVC 0x8A /* R FIFO Avail Cnt/Identify Msg */
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#define MSG_IDENTIFY_LUNMASK 0x07
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#define TUL_STIMO 0x8A /* W Sel/Resel Time Out Register */
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#define STIMO_250MS 153 /* in units of 1.6385us */
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#define TUL_SDATI 0x8B /* R SCSI Bus contents */
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#define TUL_SDAT0 0x8B /* W SCSI Data Out */
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#define TUL_SFIFO 0x8C /* R/W FIFO */
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#define TUL_SSIGI 0x90 /* R SCSI signal in */
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#define REQ 0x80 /* REQ signal */
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#define ACK 0x40 /* ACK signal */
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#define BSY 0x20 /* BSY signal */
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#define SEL 0x10 /* SEL signal */
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#define ATN 0x08 /* ATN signal */
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#define MSG 0x04 /* MSG signal */
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#define CD 0x02 /* C/D signal */
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#define IO 0x01 /* I/O signal */
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#define TUL_SSIGO 0x90 /* W SCSI signal out */
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#define TUL_SCMD 0x91 /* R/W SCSI Command */
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#define NO_OP 0x00 /* Place Holder for tulip_wait() */
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#define SEL_NOATN 0x01 /* Select w/o ATN Sequence */
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#define XF_FIFO_OUT 0x03 /* FIFO Xfer Infomation out */
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#define MSG_ACCEPT 0x0F /* Message Accept */
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#define SEL_ATN 0x11 /* Select w ATN Sequence */
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#define SEL_ATNSTOP 0x12 /* Select w ATN & Stop Sequence */
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#define SELATNSTOP 0x1E /* Select w ATN & Stop Sequence */
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#define SEL_ATN3 0x31 /* Select w ATN3 Sequence */
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#define XF_DMA_OUT 0x43 /* DMA Xfer Infomation out */
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#define EN_RESEL 0x80 /* Enable Reselection */
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#define XF_FIFO_IN 0x83 /* FIFO Xfer Infomation in */
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#define CMD_COMP 0x84 /* Command Complete Sequence */
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#define XF_DMA_IN 0xC3 /* DMA Xfer Infomation in */
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#define TUL_STEST0 0x92 /* R/W Test0 */
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#define TUL_STEST1 0x93 /* R/W Test1 */
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/*
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2001-07-27 20:16:34 +04:00
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* Tulip (aka inic-940/950) DMA Registers
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2001-06-03 17:43:45 +04:00
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*/
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#define TUL_DXPA 0xC0 /* R/W DMA Xfer Physcl Addr 0-31*/
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#define TUL_DXPAE 0xC4 /* R/W DMA Xfer Physcl Addr 32-63*/
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#define TUL_DCXA 0xC8 /* R DMA Curr Xfer Physcl Addr 0-31*/
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#define TUL_DCXAE 0xCC /* R DMA Curr Xfer Physcl Addr 32-63*/
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#define TUL_DXC 0xD0 /* R/W DMA Xfer Counter */
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#define TUL_DCXC 0xD4 /* R DMA Current Xfer Counter */
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#define TUL_DCMD 0xD8 /* R/W DMA Command Register */
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#define SGXFR 0x80 /* Scatter/Gather Xfer */
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#define RSVD 0x40 /* Reserved - always reads as 0 */
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#define XDIR 0x20 /* Xfer Direction 0/1 = out/in */
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#define BMTST 0x10 /* Bus Master Test */
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#define CLFIFO 0x08 /* Clear FIFO */
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#define ABTXFR 0x04 /* Abort Xfer */
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#define FRXFR 0x02 /* Force Xfer */
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#define STRXFR 0x01 /* Start Xfer */
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#define TUL_ISTUS0 0xDC /* R/W Interrupt Status Register */
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#define DGINT 0x80 /* DMA Global Interrupt */
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#define RSVRD0 0x40 /* Reserved */
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#define RSVRD1 0x20 /* Reserved */
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#define SCMP 0x10 /* SCSI Complete */
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#define PXERR 0x08 /* PCI Xfer Error */
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#define DABT 0x04 /* DMA Xfer Aborted */
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#define FXCMP 0x02 /* Forced Xfer Complete */
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#define XCMP 0x01 /* Bus Master Xfer Complete */
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#define TUL_ISTUS1 0xDD /* R DMA status Register */
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#define SCBSY 0x08 /* SCSI Busy */
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#define FFULL 0x04 /* FIFO Full */
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#define FEMPT 0x02 /* FIFO Empty */
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#define XPEND 0x01 /* Xfer pending */
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#define TUL_IMSK 0xE0 /* R/W Interrupt Mask Register */
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#define MSCMP 0x10 /* Mask SCSI Complete */
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#define MPXFER 0x08 /* Mask PCI Xfer Error */
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#define MDABT 0x04 /* Mask Bus Master Abort */
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#define MFCMP 0x02 /* Mask Force Xfer Complete */
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#define MXCMP 0x01 /* Mask Bus Master Xfer Complete */
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#define MASK_ALL (MXCMP | MFCMP | MDABT | MPXFER | MSCMP)
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#define TUL_DCTRL0 0xE4 /* R/W DMA Control Register */
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#define SXSTP 0x80 /* SCSI Xfer Stop */
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#define RPMOD 0x40 /* Reset PCI Module */
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#define RSVRD2 0x20 /* SCSI Xfer Stop */
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#define PWDWN 0x10 /* Power Down */
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#define ENTM 0x08 /* Enable SCSI Terminator Low */
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#define ENTMW 0x04 /* Enable SCSI Terminator High */
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#define DISAFC 0x02 /* Disable Auto Clear */
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#define LEDCTL 0x01 /* LED Control */
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#define TUL_DCTRL1 0xE5 /* R/W DMA Control Register 1 */
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#define SDWS 0x01 /* SCSI DMA Wait State */
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#define TUL_DFIFO 0xE8 /* R/W DMA FIFO */
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#define TUL_WCTRL 0xF7 /* ?/? Bus master wait state control */
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#define TUL_DCTRL 0xFB /* ?/? DMA delay control */
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