322 lines
10 KiB
C
322 lines
10 KiB
C
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/* $NetBSD: gemvar.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
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/*
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*
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IF_GEMVAR_H
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#define _IF_GEMVAR_H
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#include "rnd.h"
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#include <sys/queue.h>
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#include <sys/callout.h>
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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/*
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* Misc. definitions for the Sun ``Gem'' Ethernet controller family driver.
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*/
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/*
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* Transmit descriptor list size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet.
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*/
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#define GEM_NTXSEGS 16
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#define GEM_TXQUEUELEN 64
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#define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
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#define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
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#define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
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/*
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* Receive descriptor list size. We have one Rx buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define GEM_NRXDESC 64
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#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
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#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
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/*
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* Control structures are DMA'd to the GEM chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct gem_control_data {
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/*
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* The transmit descriptors.
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*/
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struct gem_desc gcd_txdescs[GEM_NTXDESC];
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/*
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* The receive descriptors.
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*/
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struct gem_desc gcd_rxdescs[GEM_NRXDESC];
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};
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#define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
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#define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
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#define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
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/*
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* Software state for transmit jobs.
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*/
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struct gem_txsoft {
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struct mbuf *txs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t txs_dmamap; /* our DMA map */
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int txs_firstdesc; /* first descriptor in packet */
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int txs_lastdesc; /* last descriptor in packet */
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int txs_ndescs; /* number of descriptors */
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SIMPLEQ_ENTRY(gem_txsoft) txs_q;
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};
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SIMPLEQ_HEAD(gem_txsq, gem_txsoft);
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/*
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* Software state for receive jobs.
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*/
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struct gem_rxsoft {
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struct mbuf *rxs_mbuf; /* head of our mbuf chain */
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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};
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/*
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* Table which describes the transmit threshold mode. We generally
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* start at index 0. Whenever we get a transmit underrun, we increment
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* our index, falling back if we encounter the NULL terminator.
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*/
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struct gem_txthresh_tab {
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u_int32_t txth_opmode; /* OPMODE bits */
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const char *txth_name; /* name of mode */
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};
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/*
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* Some misc. statics, useful for debugging.
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*/
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struct gem_stats {
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u_long ts_tx_uf; /* transmit underflow errors */
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u_long ts_tx_to; /* transmit jabber timeouts */
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u_long ts_tx_ec; /* excessve collision count */
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u_long ts_tx_lc; /* late collision count */
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};
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/*
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* Software state per device.
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*/
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struct gem_softc {
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struct device sc_dev; /* generic device information */
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struct ethercom sc_ethercom; /* ethernet common data */
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struct mii_data sc_mii; /* MII media control */
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#define sc_media sc_mii.mii_media/* shorthand */
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struct callout sc_tick_ch; /* tick callout */
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/* The following bus handles are to be provided by the bus front-end */
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bus_space_tag_t sc_bustag; /* bus tag */
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bus_dma_tag_t sc_dmatag; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dma handle */
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bus_space_handle_t sc_h; /* bus space handle for all regs */
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#if 0
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/* The following may be needed for SBus */
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bus_space_handle_t sc_seb; /* HME Global registers */
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bus_space_handle_t sc_erx; /* HME ERX registers */
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bus_space_handle_t sc_etx; /* HME ETX registers */
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bus_space_handle_t sc_mac; /* HME MAC registers */
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bus_space_handle_t sc_mif; /* HME MIF registers */
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#endif
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int sc_burst; /* DVMA burst size in effect */
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int sc_phys[2]; /* MII instance -> PHY map */
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int sc_mif_config; /* Selected MII reg setting */
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int sc_pci; /* XXXXX -- PCI buses are LE. */
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void *sc_sdhook; /* shutdown hook */
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void *sc_powerhook; /* power management hook */
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struct gem_stats sc_stats; /* debugging stats */
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/*
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* Ring buffer DMA stuff.
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*/
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bus_dma_segment_t sc_cdseg; /* control data memory */
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int sc_cdnseg; /* number of segments */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
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struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
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/*
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* Control data structures.
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*/
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struct gem_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->gcd_txdescs
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#define sc_rxdescs sc_control_data->gcd_rxdescs
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int sc_txfree; /* number of free Tx descriptors */
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int sc_txnext; /* next ready Tx descriptor */
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u_int32_t sc_tdctl_ch; /* conditional desc chaining */
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u_int32_t sc_tdctl_er; /* conditional desc end-of-ring */
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u_int32_t sc_setup_fsls; /* FS|LS on setup descriptor */
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struct gem_txsq sc_txfreeq; /* free Tx descsofts */
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struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
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int sc_rxptr; /* next ready RX descriptor/descsoft */
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/* ========== */
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int sc_inited;
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int sc_flags;
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int sc_debug;
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void *sc_sh; /* shutdownhook cookie */
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u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */
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/* Special hardware hooks */
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void (*sc_hwreset) __P((struct gem_softc *));
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void (*sc_hwinit) __P((struct gem_softc *));
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#if NRND > 0
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rndsource_element_t rnd_source;
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#endif
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};
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/* sc_flags */
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#define GEMF_WANT_SETUP 0x00000001 /* want filter setup */
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#define GEMF_DOING_SETUP 0x00000002 /* doing multicast setup */
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#define GEMF_HAS_MII 0x00000004 /* has media on MII */
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#define GEMF_IC_FS 0x00000008 /* IC bit on first tx seg */
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#define GEMF_MRL 0x00000010 /* memory read line okay */
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#define GEMF_MRM 0x00000020 /* memory read multi okay */
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#define GEMF_MWI 0x00000040 /* memory write inval okay */
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#define GEMF_AUTOPOLL 0x00000080 /* chip supports auto-poll */
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#define GEMF_LINK_UP 0x00000100 /* link is up (non-MII) */
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#define GEMF_LINK_VALID 0x00000200 /* link state valid */
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#define GEMF_DOINGAUTO 0x00000400 /* doing autoneg (non-MII) */
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#define GEMF_ATTACHED 0x00000800 /* attach has succeeded */
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#define GEMF_ENABLED 0x00001000 /* chip is enabled */
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#define GEMF_BLE 0x00002000 /* data is big endian */
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#define GEMF_DBO 0x00004000 /* descriptor is big endian */
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#define GEM_IS_ENABLED(sc) ((sc)->sc_flags & GEMF_ENABLED)
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/*
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* This macro returns the current media entry for *non-MII* media.
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*/
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#define GEM_CURRENT_MEDIA(sc) \
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(IFM_SUBTYPE((sc)->sc_mii.mii_media.ifm_cur->ifm_media) != IFM_AUTO ? \
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(sc)->sc_mii.mii_media.ifm_cur : (sc)->sc_nway_active)
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/*
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* This macro determines if a change to media-related OPMODE bits requires
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* a chip reset.
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*/
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#define GEM_MEDIA_NEEDSRESET(sc, newbits) \
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(((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \
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((newbits) & OPMODE_MEDIA_BITS))
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#define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
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#define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
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#define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF)
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#define GEM_CDTXSYNC(sc, x, n, ops) \
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do { \
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int __x, __n; \
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\
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__x = (x); \
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__n = (n); \
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\
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/* If it will wrap around, sync to the end of the ring. */ \
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if ((__x + __n) > GEM_NTXDESC) { \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \
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(GEM_NTXDESC - __x), (ops)); \
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__n -= (GEM_NTXDESC - __x); \
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__x = 0; \
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} \
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\
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/* Now sync whatever is left. */ \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \
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} while (0)
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#define GEM_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops))
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#define GEM_CDSPSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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GEM_CDSPOFF, GEM_SETUP_PACKET_LEN, (ops))
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#define GEM_INIT_RXDESC(sc, x) \
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do { \
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struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
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struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
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struct mbuf *__m = __rxs->rxs_mbuf; \
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\
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__m->m_data = __m->m_ext.ext_buf; \
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__rxd->gd_addr = \
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htole64(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
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__rxd->gd_flags = \
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htole64((((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \
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& GEM_RD_BUFSIZE) | GEM_RD_OWN); \
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GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#ifdef _KERNEL
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void gem_attach __P((struct gem_softc *, const u_int8_t *));
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int gem_activate __P((struct device *, enum devact));
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int gem_detach __P((struct gem_softc *));
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int gem_intr __P((void *));
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int gem_read_srom __P((struct gem_softc *));
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int gem_srom_crcok __P((const u_int8_t *));
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int gem_isv_srom __P((const u_int8_t *));
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int gem_isv_srom_enaddr __P((struct gem_softc *, u_int8_t *));
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int gem_parse_old_srom __P((struct gem_softc *, u_int8_t *));
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int gem_mediachange __P((struct ifnet *));
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void gem_mediastatus __P((struct ifnet *, struct ifmediareq *));
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void gem_config __P((struct gem_softc *));
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void gem_reset __P((struct gem_softc *));
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int gem_intr __P((void *));
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#endif /* _KERNEL */
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#endif
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