155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)bsd_audioreg.h 8.1 (Berkeley) 6/11/93
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*
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* from: Header: bsd_audioreg.h,v 1.3 92/06/07 21:12:50 mccanne Exp (LBL)
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* $Id: bsd_audioreg.h,v 1.1 1993/10/02 10:22:34 deraadt Exp $
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*/
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/*
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* Bit encodings for chip commands from "Microprocessor Access Guide for
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* Indirect Registers", p.19 Am79C30A/32A Advanced Micro Devices spec
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* sheet (preliminary).
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*
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* Indirect register numbers (the value written into cr to select a given
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* chip registers) have the form AMDR_*. Register fields look like AMD_*.
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*/
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struct amd7930 {
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u_char cr; /* command register (wo) */
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#define ir cr /* interrupt register (ro) */
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u_char dr; /* data register (rw) */
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u_char dsr1; /* D-channel status register 1 (ro) */
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u_char der; /* D-channel error register (ro) */
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u_char dctb; /* D-channel transmit register (wo) */
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#define dcrb dctb /* D-channel receive register (ro) */
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u_char bbtb; /* Bb-channel transmit register (wo) */
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#define bbrb bbtb /* Bb-channel receive register (ro) */
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u_char bctb; /* Bc-channel transmit register (wo) */
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#define bcrb bctb /* Bc-channel receive register (ro) */
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u_char dsr2; /* D-channel status register 2 (ro) */
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};
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#define AMDR_INIT 0x21
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#define AMD_INIT_PMS_IDLE 0x00
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#define AMD_INIT_PMS_ACTIVE 0x01
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#define AMD_INIT_PMS_ACTIVE_DATA 0x02
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#define AMD_INIT_INT_DISABLE (0x01 << 2)
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#define AMD_INIT_CDS_DIV2 (0x00 << 3)
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#define AMD_INIT_CDS_DIV1 (0x01 << 3)
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#define AMD_INIT_CDS_DIV4 (0x02 << 3)
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#define AMD_INIT_AS_RX (0x01 << 6)
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#define AMD_INIT_AS_TX (0x01 << 7)
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#define AMDR_LIU_LSR 0xa1
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#define AMDR_LIU_LPR 0xa2
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#define AMDR_LIU_LMR1 0xa3
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#define AMDR_LIU_LMR2 0xa4
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#define AMDR_LIU_2_4 0xa5
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#define AMDR_LIU_MF 0xa6
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#define AMDR_LIU_MFSB 0xa7
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#define AMDR_LIU_MFQB 0xa8
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#define AMDR_MUX_MCR1 0x41
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#define AMDR_MUX_MCR2 0x42
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#define AMDR_MUX_MCR3 0x43
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#define AMD_MCRCHAN_NC 0x00
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#define AMD_MCRCHAN_B1 0x01
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#define AMD_MCRCHAN_B2 0x02
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#define AMD_MCRCHAN_BA 0x03
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#define AMD_MCRCHAN_BB 0x04
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#define AMD_MCRCHAN_BC 0x05
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#define AMD_MCRCHAN_BD 0x06
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#define AMD_MCRCHAN_BE 0x07
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#define AMD_MCRCHAN_BF 0x08
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#define AMDR_MUX_MCR4 0x44
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#define AMD_MCR4_INT_ENABLE (1 << 3)
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#define AMD_MCR4_SWAPBB (1 << 4)
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#define AMD_MCR4_SWAPBC (1 << 5)
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#define AMDR_MUX_1_4 0x45
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#define AMDR_MAP_X 0x61
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#define AMDR_MAP_R 0x62
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#define AMDR_MAP_GX 0x63
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#define AMDR_MAP_GR 0x64
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#define AMDR_MAP_GER 0x65
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#define AMDR_MAP_STG 0x66
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#define AMDR_MAP_FTGR 0x67
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#define AMDR_MAP_ATGR 0x68
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#define AMDR_MAP_MMR1 0x69
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#define AMD_MMR1_ALAW 0x01
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#define AMD_MMR1_GX 0x02
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#define AMD_MMR1_GR 0x04
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#define AMD_MMR1_GER 0x08
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#define AMD_MMR1_X 0x10
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#define AMD_MMR1_R 0x20
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#define AMD_MMR1_STG 0x40
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#define AMD_MMR1_LOOP 0x80
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#define AMDR_MAP_MMR2 0x6a
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#define AMD_MMR2_AINB 0x01
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#define AMD_MMR2_LS 0x02
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#define AMD_MMR2_DTMF 0x04
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#define AMD_MMR2_GEN 0x08
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#define AMD_MMR2_RNG 0x10
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#define AMD_MMR2_DIS_HPF 0x20
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#define AMD_MMR2_DIS_AZ 0x40
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#define AMDR_MAP_1_10 0x6b
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#define AMDR_DLC_FRAR123 0x81
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#define AMDR_DLC_SRAR123 0x82
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#define AMDR_DLC_TAR 0x83
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#define AMDR_DLC_DRLR 0x84
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#define AMDR_DLC_DTCR 0x85
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#define AMDR_DLC_DMR1 0x86
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#define AMDR_DLC_DMR2 0x87
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#define AMDR_DLC_1_7 0x88
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#define AMDR_DLC_DRCR 0x89
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#define AMDR_DLC_RNGR1 0x8a
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#define AMDR_DLC_RNGR2 0x8b
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#define AMDR_DLC_FRAR4 0x8c
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#define AMDR_DLC_SRAR4 0x8d
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#define AMDR_DLC_DMR3 0x8e
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#define AMDR_DLC_DMR4 0x8f
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#define AMDR_DLC_12_15 0x90
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#define AMDR_DLC_ASR 0x91
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